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AMD Geode™ LX Processors Data Book 175
CPU Core Register Descriptions
33234H
5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR)
The SNOOP_MSR provides a mechanism for injecting a “snoop-for-write” request into the memory subsystem. Both the I
and D caches are snooped for the specified physical address. A hit to a dirty line in the D cache results in a writeback fol-
lowed by the line being invalidated. A hit to a clean line results in only an invalidation. The SNOOP_MSR is write-only - the
read value is undefined. There is no indication as to whether the snoop hit in the caches.
5.5.2.80 L1 Data TLB Index Register (L1DTLB_INDEX_MSR)
MSR Address 00001894h
Typ e WO
Reset Value 00000000_xxxxxxxxh
SNOOP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
SNOOP_ADD
SNOOP_MSR Bit Descriptions
Bit Name Description
63:32 RSVD Reserved (Write Only). Write as 0.
31:0 SNOOP_ADD Cache Snoop Address (Write Only). Physical address to snoop in the caches. A hit to a
dirty line results in a writeback followed by an invalidation. A hit to a clean line results in
an invalidation only. Both the data and instruction caches are snooped.
MSR Address 00001898h
Typ e R /W
Reset Value 00000000_00000000h
L1DTLB_INDEX_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD INDEX
L1DTLB_INDEX_MSR Bit Descriptions
Bit Name Description
63:3 RSVD (RO) Reserved (Read Only).
2:0 INDEX L1 Data TLB Index. Index of L1 Data TLB entry to access. Post increments on each
access to L1TLB_ENTRY_I_MSR (MSR 0000189Bh).