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AMD Geode™ LX Processors Data Book 327
Display Controller Register Descriptions
33234H
6.6.5 Timing Registers
The DC timing registers control the generation of sync, blanking, and active display regions. These registers are generally
programmed by the BIOS from an INT 10h call or by the extended mode driver from a display timing file.
Example: To display a 1024x768 graphics (frame buffer) image on a 720x483/59.94 television. The DC CRTC settings are
as follows:
Note: The above timings are based on tables B.1 and B.2 in the ANSI/SMTPE 293M-1996 spec. They assume that the
frame buffer image should be displayed over the entire 720x483 screen, with no additional border.
The DC_GFX_SCALE (DC Memory Offset 090h) register would be set up to scale the 1024x768 image to a 720x483
frame:
v_scale = (768/(483-1)) = 1.593360995...
h_scale = (1024/(720 - 1)) = 1.424200278...
DC_GFX_SCALE = 65F9_5B26h
(v_scale = 1.593322754; h_scale = 1.424194336)
In addition, the FILT_ENA and INTL_EN bits would be set (DC Memory Offset 94h[12,11] = 11), and the filter coefficients
would be programmed. This example also presumes that the FLICK_EN bit is set (DC Memory Offset 0D4h[24] = 1).
Because the output is to be interlaced, the flicker filter can be used. (Use of the flicker filter is not required.) For information
on the configuration bits for the flicker filter, see "DC GenLock Control (DC_GENLK_CTL)" on page 350.
DC_H_ACTIVE_TIMING (040h) = 0x035A_02D0 // h_total = 858; h_active = 720
DC_H_BLANK_TIMING (044h) = 0x35A_02D0 // h_blank_start = 720; h_blank_end=858 -- no overscan
DC_H_SYNC_TIMING (048h) = 0x031F_02E0 // h_sync start = 736; h_sync_end = 799
DC_V_ACTIVE_TIMING (050h) = 0x0106_00F1 // v_total = 262 (even) 263(odd); v_active = 241 (even & odd)
DC_V_BLANK_TIMING (054h) = 0x0106_00F1 // v_blank_start = 241; v_blank_end = 262 -- no overscan
DC_V_SYNC_TIMING (058h) = 0x00F6_00F5 // v_sync_start = 245; vsync_end = 246
DC_V_ACTIVE_EVEN_TIMING (0E4h) =
0x0105_00F0
// v_total = 261; v_active = 240
DC_V_BLANK_EVEN_TIMING (0E8h) =
0x0105_00F0
// v_blank_start = 240; v_blank_end = 261
DC_V_SYNC_EVEN_TIMING (0ECh) = 0x00F6_00F5 // v_sync_start = 245; v_sync_end = 246
DC_B_ACTIVE (05Ch) = 03FF_02FFh // frame buffer size1024x768