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AMD Geode™ LX Processors Data Book 157
CPU Core Register Descriptions
33234H
5.5.2.60 L1 Instruction TLB Entry MSRs
ITB Entry MSR (ITB_ENTRY_MSR)
ITB Entry with Increment MSR (ITB_ENTRY_I_MSR)
ITB L0 Cache Entry MSR (ITB_L0_ENTRY_MSR)
MSR Address 00001722h
Typ e R /W
Reset Value xxxxxxxx_xxxxxxxxh
MSR Address 00001723h
Typ e R /W
Reset Value xxxxxxxx_xxxxxxxxh
MSR Address 00001724h
Type R /W
Reset Value xxxxxxxx_xxxxxxxxh
ITB_ENTRY_MSR, ITB_ENTRY_I_MSR, ITB_L0_ENTRY_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LINADDR RSVD
313029282726252423222120191817161514131211109876543210
PHYSADDR WS RSVD CD
RSVD
US
RSVD
V
ITB_ENTRY_MSR, ITB_ENTRY_I_MSR, ITB_L0_ENTRY_MSR Bit Descriptions
Bits Name Description
63:44 LINADDR Linear Address.
43:32 RSVD (RO) Reserved (Read Only). (Default = 0)
31:12 PHYSADDR Physical Address.
11 WS Write Serialize Property.
0: Not write serialized. (Default)
1: Write serialized.
10:5 RSVD (RO) Reserved (Read Only). (Default = 0)
4CD Cache Disable.
0: Cache enabled.
1: Cache disabled.
3 RSVD (RO) Reserved (Read Only). (Default = 0)
2US User Access Privileges.
0: Supervisor.
1: User.
1 RSVD (RO) Reserved (Read Only). (Default = 0)
0V Valid Bit.
0: Not valid. (Default)
1: Valid.