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AMD Geode™ LX Processors Data Book 577
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16.1.5 GLD Power Management MSR (GLD_MSR_PM)
6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
This register is for AMD use only and should not be written to.
MSR Address 50002004h
Typ e R /W
Reset Value 00000000_00000015h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
PM2
RSVD
PM1
RSVD
PM0
GLD_MSR_PM Bit Descriptions
Bit Name Description
63:5 RSVD (RO) Reserved (Read Only). Reserved for future use.
4PM2 Power Mode 2. Power mode for PCI-fast clock domain.
0: Disable clock gating. Clocks are always ON.
1: Enable active hardware clock gating.
3 RSVD (RO) Reserved (Read Only). Reserved for future use.
2PM1 Power Mode 1. Power mode for PCI clock domain.
0: Disable clock gating. Clocks are always ON.
1: Enable active hardware clock gating.
1 RSVD (RO) Reserved (Read Only). Reserved for future use.
0PM0 Power Mode 0. Power mode for GLIU clock domain.
0: Disable clock gating. Clocks are always ON.
1: Enable active hardware clock gating.
MSR Address 50002005h
Typ e R /W
Reset Value 00000000_00000000h