Filter
Top Products
AMD Geode™ LX Processors Data Book 129
CPU Core Register Descriptions
33234H
5.5.2.21 Debug Management Interrupt (DMI) Control Register
MSR Address 00001302h
Typ e R /W
Reset Value 00000000_00000000h
DMI Control Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
DMI_TF
DMI_STALL
DMM_SUSP
DMI_TSS
DMM_CACHE
DMI_ICEBP
DMI_DBG
DMI_EXT
DMI_GPF
DMI_INST
DMI Control Register Bit Descriptions
Bit Name Description
63:10 RSVD Reserved. Write as read.
9DMI_TF DMI Trap Flag.
0: Disable DMI single stepping.
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
tion. If DMI_STALL is 1, debug stall occurs after the successful execution of each
instruction.
8DMI_STALL DMI Stall.
0: If not in DMM, DMI conditions cause DMIs.
1: DMI conditions cause a debug stall.
7 DMM_SUSP Enable SUSP# during DMM. Enable SUSP# during DMM mode.
0: Disable.
1: Enable.
6DMI_TSS Task Switch Debug Fault Control.
0: Task switch debug faults cause debug exceptions.
1: Task switch debug exceptions cause DMIs when not in DMM.
5 DMM_CACHE Cache Control during DMM.
0: Do not change CR0 CD and NW bits when entering DMM.
1: Set CR0, CD and NW bits when entering DMM
.
See Table 5-10 "CR0 Bit Descriptions" on page 96 for CD and NW bit descriptions.
4 DMI_ICEBP Enable DMIs on ICEBP (F1) Instructions.
0: Disable.
1: Enable.
3DMI_DBG Enable Replacing Debug Exceptions as DMIs.
0: Disable.
1: Enable.
2 DMI_EXT Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (ball AB2) when not
in DMM.
0: Disable.
1: Enable.