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AMD Geode™ LX Processors Data Book 149
CPU Core Register Descriptions
33234H
5.5.2.49 Extended Flags MSR (EFLAG_MSR)
5.5.2.50 Control Register 0 MSR (CR0_MSR)
This is the standard x86 Control Register 0 (CR0). CR1, CR2, CR3, and CR4 are located at MSRs 00001881h-00001884h
(see Section 5.5.2.74 on page 172). The contents of CR0-CR4 should only be accessed using the MOV instruction. They
are mentioned here for completeness only. See Section 5.4.1 “Control Registers” on page 95 for bit descriptions.
MSR Address 00001418h
Typ e R /W
Reset Value 00000000_00000002h
EFLAG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD (0) ID RSVD
(0)
AC VM RF
RSVD (0)
NT IOPL OF DF IF TF SF ZF
RSVD (0)
AF
RSVD (0)
PF
RSVD (1)
CF
EFLAG_MSR Bit Descriptions
Bit Name Description
63:22 RSVD Reserved. (Default = 0)
21 ID Identification Flag. (Default = 0)
20:19 RSVD Reserved. (Default = 0)
18 AC Alignment Check Flag. (Default = 0)
17 VM Virtual 8086 Flag. (Default = 0)
16 RF Resume Flag. Disable instruction address breakpoints. (Default = 0)
15 RSVD Reserved. (Default = 0)
14 NT Nested Task Flag. (Default = 0)
13:12 IOPL Input/Output Privilege Level. (Default = 0)
11 OF Overflow Flag. (Default = 0)
10 DF Repeated-String Direction Flag. (Default = 0)
9IF Eternal Maskable Interrupt Enable. (Default = 0)
8TF Single-Step Trap Flag. (Default = 0)
7SF Sign Flag. (Default = 0)
6ZF Zero Flag. (Default = 0)
5 RSVD Reserved. (Default = 0)
4AF Auxiliary Carry Flag. (Default = 0)
3 RSVD Reserved. (Default = 0)
2PF Parity Flag. (Default = 0)
1 RSVD Reserved. (Default = 1)
0CF Carry Flag. (Default = 1)
MSR Address 00001420h
Typ e R /W
Reset Value 00000000_60000010h