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128 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.20 SMM Control MSR (SMM_CTL_MSR)
MSR Address 00001301h
Typ e R /W
Reset Value 00000000_00000000h
SMM_CTL_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
SMI_EXTL
SMI_IO
SMI_INST
SMM_NEST
SMM_SUSP
SMM_NMI
SMM_CTL_MSR Bit Descriptions
Bit Name Description
63:6 RSVD (RO) Reserved (Read Only).
5 SMI_EXTL Enable External ASMI Pin. Enable external asynchronous SMIs.
0: Disable.
1: Enable.
4SMI_IO Enable I/O Generated SMI. Enable SMIs caused by an I/O instruction.
0: Disable.
1: Enable.
3SMI_INST Enable SMI Instructions. Enable SMI instructions: SMINT, RSM, SVDC, RSDC,
SVLDT, RSLDT, SVTS, RSTS. If not enabled, executing an SMI instruction causes an
invalid operation fault.
0: Disable.
1: Enable.
2 SMM_NEST Enable SMI Nesting. Enable non-software SMIs during SMM mode.
0: Disable.
1: Enable.
1SMM_SUSP Enable Suspend during SMM. Enable Suspend during SMM mode.
0: Disable.
1: Enable.
0 SMM_NMI Enable Non-Maskable Interrupts during SMM. Enable NMI during SMM mode.
0: Disable.
1: Enable.