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624 AMD Geode™ LX Processors Data Book
Instruction Set
33234H
8.1.4 reg Field
The reg field (Table 8-10) determines which general registers are to be used. The selected register is dependent on
whether a 16-bit or 32-bit operation is current and on the status of the w bit.
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)
The sreg2 field (Table 8-11) is a 2-bit field that allows one of the four 286-type segment registers to be specified.
8.1.4.2 sreg3 Field (FS and GS Segment Register Selection)
The sreg3 field (Table 8-12) is 3-bit field that is similar to the sreg2 field, but allows use of the FS and GS segment registers.
Table 8-10. reg Field
reg
16-Bit Operation 32-Bit Operation
w = 0 w = 1 w = 0 w = 1
000 AL AX AL EAX
001 CL CX CL ECX
010 DL DX DL EDX
011 BL BX BL EBX
100 AH SP AH ESP
101 CH BP CH EBP
110 DH SI DH ESI
111 BH DI BH EDI
Table 8-11. sreg2 Field Encoding
sreg2 Field Segment Register Selected
00 ES
01 CS
10 SS
11 DS
Table 8-12. sreg3 Field (FS and GS Segment Register Selection)
sreg3 Field Segment Register Selected
000 ES
001 CS
010 SS
011 DS
100 FS
101 GS
110 Undefined
111 Undefined