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572 AMD Geode™ LX Processors Data Book
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16 GeodeLink™ PCI Bridge Register Descriptions
All GeodeLink™ PCI Bridge (GLPCI) registers are Model
Specific Registers (MSRs) and are accessed via the
RDMSR and WRMSR instructions.
The registers associated with the GLPCI are the Standard
GeodeLink Device (GLD) MSRs and GLPCI Specific
MSRs. Table 6-91 and Table 6-92 are register summary
tables that include reset values and page references where
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
Table 6-91. Standard GeodeLink™ Device MSRs Summary
MSR
Address Type Register Name Reset Value Reference
50002000h RO GLD Capabilities MSR (GLD_MSR_CAP) 00000000_001054xxh Page 574
50002001h R/W GLD Master Configuration MSR
(GLD_MSR_CONFIG)
00000000_00000000h Page 574
50002002h R/W GLD SMI MSR (GLD_MSR_SMI) 00000000_0000003Fh Page 575
50002003h R/W GLD Error MSR (GLD_MSR_ERROR) 00000000_0000003Fh Page 576
50002004h R/W GLD Power Management MSR
(GLD_MSR_PM)
00000000_00000015h Page 577
50002005h R/W GLD Diagnostic MSR (GLD_MSR_DIAG) 00000000_00000000h Page 577
Table 6-92. GLPCI Specific Registers Summary
MSR
Address Type Register Name Reset Value Reference
50002010h R/W GLPCI Global Control (GLPCI_CTRL) 44000000_00000000h Page 578
50002011h R/W GLPCI Arbiter Control (GLPCI_ARB) 00000000_00000000h Page 581
50002012h R/W GLPCI VPH / PCI Configuration Cycle Con-
trol (GLPCI_PBUS)
00FF0000_00000000h Page 584
50002013h R/W GLPCI Debug Packet Configuration
(GLPCI_DEBUG)
00000000_00000000h Page 584
50002014h R/W GLPCI Fixed Region Enables
(GLPCI_REN)
00000000_00000000h Page 584
50002015h R/W GLPCI Fixed Region Configuration A0-BF
(GLPCI_A0)
00000000_00000000h Page 585
50002016h R/W GLPCI Fixed Region Configuration C0-DF
(GLPCI_C0)
00000000_00000000h Page 586
50002017h R/W GLPCI Fixed Region Configuration E0-FF
(GLPCI_E0)
00000000_00000000h Page 587
50002018h R/W GLPCI Memory Region 0 Configuration
(GLPCI_R0)
00000000_00000000h Page 588
50002019h R/W GLPCI Memory Region 1 Configuration
(GLPCI_R1)
00000000_00000000h Page 589
5000201Ah R/W GLPCI Memory Region 2 Configuration
(GLPCI_R2)
00000000_00000000h Page 590
5000201Bh R/W GLCPI Memory Region 3 Configuration
(GLPCI_R3)
00000000_00000000h Page 591
5000201Ch R/W GLCPI Memory Region 4 Configuration
(GLPCI_R4)
00000000_00000000h Page 592