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176 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR)
MSR Address 00001899h
Typ e R /W
Reset Value 00000000_00000000h
L1DTLB_LRU_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD LRU
L1DTLB_LRU_MSR Bit Descriptions
Bits Name Description
63:18 RSVD (RO) Reserved (Read Only).
17:0 LRU Least Recently Used Value.
Bit 17: Entries 8-11 more recent than entries 12-15.
Bit 16: Entries 4-7 more recent than entries 12-15.
Bit 15: Entries 4-7 more recent than entries 8-11.
Bit 14: Entries 0-3 more recent than entries 12-15.
Bit 13: Entries 0-3 more recent than entries 8-11.
Bit 12: Entries 0-3 more recent than entries 4-7.
Bit 11: Entries 12/13 more recent than entries 14/15.
Bit 10: Entries 8/9 more recent than entries 10/11.
Bit 9: Entries 4/5 more recent than entries 6/7.
Bit 8: Entries 0/1 more recent than entries 2/3.
Bit 7: Entry 14 more recent than entry 15.
Bit 6: Entry 12 more recent than entry 13.
Bit 5: Entry 10 more recent than entry 11.
Bit 4: Entry 8 more recent than entry 9.
Bit 3: Entry 6 more recent than entry 7.
Bit 2: Entry 4 more recent than entry 5.
Bit 1: Entry 2 more recent than entry 3.
Bit 0: Entry 0 more recent than entry 1.
0: False (Default)
1: True