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192 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.102 L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR)
MSR Address 00001927h
Typ e R /W
Reset Value 00000000_00000000h
L2_TRTMNT_CTL_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
TAG_ST_RST_CODE
RSVD
IMEVCT_INVAL_CODE
RSVD
L2_INVAL_CODE
RSVD
TAG_ST_RST_EN
IMEVCT_INVAL_EN
L2_INVAL_EN
L2_TRTMNT_CTL_MSR Bit Descriptions
Bit Name Description
63:19 RSVD Reserved.
18:16 TAG_ST_RST_
CODE
L2 Cache Tag State Machine Reset Code. If TAG_ST_RST_ENA (bit 2) is set, the
code on the treatment bus forces the tag state machine to reset. (Caution: Extremely
destructive - use only to poke around on hard hangs.) (Default = 0)
15 RSVD Reserved.
14:12 IMEVCT_INVAL
_CODE
Instruction Memory Subsystem Eviction Invalidate Code. If IMEVCT_INVAL_ENA
(bit 1) is set, the code on the treatment bus forces invalidation of the IM eviction buffer.
(Default = 0)
11 RSVD Reserved.
10:8 L2_INVAL_
CODE
L2 Cache Invalidate Code. If L2_INVAL_ENA (bit 0) is set, the code on the treatment
bus forces invalidation of the L2 cache. (Default = 0)
7:3 RSVD Reserved.
2TAG_ST_RST_
EN
L2 Cache Tag State Machine Reset Enable. Allows tag state machine reset through
the treatment bus.
0: Disable. (Default)
1: Enable.
1 IMEVCT_INVAL
_EN
Instruction Memory Subsystem Eviction Invalidate Enable. Allows IM eviction buffer
invalidation through the treatment bus.
0: Disable. (Default)
1: Enable.
0 L2_INVAL_EN L2 Cache Invalidate Enable. Allows L2 cache invalidation through the treatment bus.
0: Disable. (Default)
1: Enable.