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666 AMD Geode™ LX Processors Data Book
Instruction Set
33234H
1) This instruction must wait for the FPU pipeline to flush. Cycle count depends on what instructions are in the pipeline.
PXOR Bitwise XOR
MMX Register 2 to MMX Register 1 0FEF [11 mm1
mm2]
MMX reg 1 [qword] --- MMX reg 1 [qword], <--- logic exclusive
OR MMX reg 2 [qword]
2
Memory to MMX Register 0FEF [11 mm reg] MMX reg [qword] --- memory64 [qword], <--- logic exclusive
OR MMX reg [qword]
2
SFENCE Store Fence
0FAE [mod 111 r/m]
Table 8-28. MMX™ Instruction Set (Continued)
MMX™ Instructions Opcode Operation Clock Ct Notes