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AMD Geode™ LX Processors Data Book 179
CPU Core Register Descriptions
33234H
5.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR)
15:6 RSVD (RO) Reserved (Read Only). (Default = 0)
5:0 INDEX DTE/PTE Index. Increments on every access to L2TLB_ENTRY_I_MSR (MSR
0000189Fh).
MSR Address 0000189Dh
Typ e R /W
Reset Value 00000000_00000000h
L2TLB_INDEX_MSR Bit Descriptions (Continued)
Bit Name Description
L2TLB_LRU_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD DTE_LRU
313029282726252423222120191817161514131211109876543210
RSVD PTE_LRU RSVD
L2WR1
L2TLB_LRU_MSR Bit Descriptions
Bits Name Description
63:53 RSVD (RO) Reserved (Read Only). (Default = 0)
52:32 DTE_LRU DTE Least Recently Used Value.
Bit 52: DTE entries 0-3 more recent than entries 4-7.
Bit 51: DTE entries 0-3 more recent than entries 8-11.
Bit 50: DTE entries 4-7 more recent than entries 8-11.
Bit 49: DTE entry 8 more recent than entry 9.
Bit 48: DTE entry 8 more recent than entry 10.
Bit 47: DTE entry 8 more recent than entry 11.
Bit 46: DTE entry 9 more recent than entry 10.
Bit 45: DTE entry 9 more recent than entry 11.
Bit 44: DTE entry 10 more recent than entry 11.
Bit 43: DTE entry 4 more recent than entry 5.
Bit 42: DTE entry 4 more recent than entry 6.
Bit 41: DTE entry 4 more recent than entry 7.
Bit 40: DTE entry 5 more recent than entry 6.
Bit 39: DTE entry 5 more recent than entry 7.
Bit 38: DTE entry 6 more recent than entry 7.
Bit 37: DTE entry 0 more recent than entry 1.
Bit 36: DTE entry 0 more recent than entry 2.
Bit 35: DTE entry 0 more recent than entry 3.
Bit 34: DTE entry 1 more recent than entry 2.
Bit 33: DTE entry 1 more recent than entry 3.
Bit 32: DTE entry 2 more recent than entry 3.
0: False (Default)
1: True
31:22 RSVD (RO) Reserved (Read Only). (Default = 0)