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174 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.78 Data Cache Tag with Increment MSR (DC_TAG_I_MSR)
Bit descriptions for this register are the same as for MSR 00001892h, except read/write of this register causes an auto-
increment on DC_INDEX_MSR (MSR 00001890h).
49:32 LRU Least Recently Used Value. (Default = 0)
Bit 49: Ways 11-8 more recent than ways 15-12.
Bit 48: Ways 7-4 more recent than ways 15-12.
Bit 47: Ways 7-4 more recent than ways 11-8.
Bit 46: Ways 3-0 more recent than ways 15-12.
Bit 45: Ways 3-0 more recent than ways 11-8.
Bit 44: Ways 3-0 more recent than ways 7-4.
Bit 43: Ways 15-14 more recent than ways 13-12.
Bit 42: Ways 11-10 more recent than ways 9-8.
Bit 41: Ways 7-6 more recent than ways 5-4.
Bit 40: Ways 3-2 more recent than ways 1-0.
Bit 39: Way 15 more recent than way 14.
Bit 38: Way 13 more recent than way 12.
Bit 37: Way 11 more recent than way 10.
Bit 36: Way 9 more recent than way 8.
Bit 35: Way 7 more recent than way 6.
Bit 34: Way 5 more recent than way 4.
Bit 33: Way 3 more recent than way 2.
Bit 32: Way 1 more recent than way 0.
0: False
1: True
31:12 TAG Tag. Cache Tag Value for line/way selected by DC_INDEX (MSR 00001890h).
(Default = 0)
11:2 RSVD (RO) Reserved (Read Only). (Default = 0)
1DIRTY Dirty. Dirty bit for line/way. (Default = 0)
WARNING: Operation is undefined if the Dirty bit is set to 1 and the Valid bit is 0.
0VALID Valid. Valid bit for the line/way selected by DC_INDEX (MSR 00001890h). (Default = 0)
MSR Address 00001893h
Typ e R /W
Reset Value 00000000_00000000h
DC_TAG_MSR Bit Descriptions (Continued)
Bits Name Description
DC_TAG_I_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD LRU
313029282726252423222120191817161514131211109876543210
TAG RSVD
DIRTY
VALID