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AMD Geode™ LX Processors Data Book 151
CPU Core Register Descriptions
33234H
8ICD Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents
of cache is not modified and no cache entry is read.
0: Use standard x86 cacheability rules. (Default)
1: Instruction cache will always generate a miss.
7TUS Translation Look-aside Buffer Updates Select. Select L1 TLB updates (not L1 TLB
evictions) to go out on the IM’s Translation Bus. Otherwise, only L1 TLB evictions go out
on IM’s Translation Bus. IM only supports either updates or evictions going out on the
bus, but not both.
0: Disable. (Default)
1: Enable.
6 RSVD Reserved. Always write zero.
5 L0D L0 Cache Disable.
0: Disable. (Default)
1: Enable.
4 L0IN L0 Cache Invalidate.
0: Disable. (Default)
1: Enable.
3 RSVD Reserved.
2 SER Serialize Cache State Machine. If this bit is set, only one outstanding request to the bus
controller is allowed at one time.
0: Disable. (Default)
1: Enable.
1FLD Flushing Disable. Disable full flushing of the IM (including outstanding bus controller
requests) on IF aborts. If this bit is disabled, the IM only aborts requests that have not
already gone out to the bus controller.
0: Enable. (Default)
1: Disable.
0TBE Treatment Bus Enable. If this bit is set, then the treatment bus from the GLCP is able to
modify the IM’s behavior.
0: Disable. (Default)
1: Enable
IM_CONFIG_MSR Bit Descriptions (Continued)
Bits Name Description