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542 AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address 4C002002h
Typ e R /W
Reset Value 00000000_0000001Fh
GLD_MSR_SMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
SMI_EXT
SMI_PML2
SMI_PMCNT
SMI_DBG
SMI_ERR
RSVD
SMI_EXT_MASK
SMI_PML2_MASK
SMI_PMCNT_MASK
SMI_DBG_MASK
SMI_ERR_MASK
GLD_MSR_SMI Bit Descriptions
Bit Name Description
63:21 RSVD Reserved.
20 SMI_EXT SMI from I/O Companion. ASMI generated when most recent serial packet had
SMI bit set. This bit ALWAYS represents the state of the SMI bit in the last serial
packet received. It cannot be written. To clear external SMI sources, proper external
controls must be sent (i.e., via the PCI bus).
19 SMI_PML2 SMI Power Management GLCP_LVL2. SSMI generated when GLCP_LVL2 (MSR
4C000019h) I/O register was read. Write 1 to clear, 0 has no effect.
18 SMI_PMCNT SMI Power Management GLCP_CNT Mask. SSMI generated when GLCP_CNT
(MSR 4C000018h) I/O register was written. Write 1 to clear, 0 has no effect.
17 SMI_DBG SMI Debug. ASMI generated due to debug event or PROCSTAT access. Write 1 to
clear, 0 has no effect.
16 SMI_ERR SMI Error. ASMI generated due to error signal. Write 1 to clear, 0 has no effect.
15:5 RSVD Reserved.
4 SMI_EXT_MASK SMI from I/O Companion Mask. If clear, enables serial packets from external
device to generate an ASMI.
3 SMI_PML2_MASK SMI Power Management GLCP_LVL2 Mask. If clear, enables power management
logic to generate an SSMI when GLCP_LVL2 I/O register (MSR 4C000019h) is read.
2 SMI_PMCNT_MASK SMI Power Management GLCP_CNT Mask. If clear, enables power management
logic to generate an SSMI when GLCP_CNT (MSR 4C000018h) I/O register is writ-
ten.
1 SMI_DBG_MASK SMI Debug Mask. If clear, enables debug logic to generate an ASMI.
0 SMI_ERR_MASK SMI Error Mask. If clear, then any GLIU device error signal (including GLCP)
causes an ASMI.