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7.6ResetController
7.6.1Power-onReset(PORPin)
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
TheresetcontrollerdetectsthedifferenttypeofresetssupportedontheC6455deviceandmanagesthe
distributionofthoseresetsthroughoutthedevice.
TheC6455devicehasseveraltypesofresets:power-onreset,warmreset,maxreset,systemreset,and
CPUreset.Table7-12explainsfurtherthetypesofreset,theresetinitiator,andtheeffectsofeachreset
onthechip.FormoreinformationontheeffectsofeachresetonthePLLcontrollersandtheirclocks,see
Section7.6.8,ResetElectricalData/Timing.
Table7-12.ResetTypes
TYPEINITIATOREFFECT(s)
Power-onResetPORpinResetstheentirechipincludingthetestandemulationlogic.
ResetseverythingexceptforthetestandemulationlogicandPLL2.
WarmResetRESETpin
EmulatorstaysaliveduringWarmReset.
MaxResetRapidIO[throughINTDST5
(1)
]SameasWarmReset.
Asystemresetmaintainsmemorycontentsanddoesnotresetthe
SystemResetEmulatortestandemulationcircuitry.Thedeviceconfigurationpinsarealso
notre-latchedandthestateoftheperipheralsisalsonotaffected.
(2)
CPULocalResetHPI/PCICPUlocalreset.
(1)INTDST5isusedgenerateaMAXresetonly.Itisnotconnectedtothedeviceinterruptcontroller.Formoredetailedinformationonthe
INTDST5,seetheTMS320C645xDSPSerialRapidI/OUser'sGuide(literaturenumberSPRU976).
(2)OntheC6455device,peripheralscanbeinoneofseveralstates.ThesestatesarelistedinTable3-4.
Power-onResetisinitiatedbythePORpinandisusedtoresettheentirechip,includingthetestand
emulationlogic.Power-onResetisalsoreferredtoasacoldresetsincethedeviceusuallygoesthrougha
power-upcycle.Duringpower-up,thePORpinmustbeasserted(drivenlow)untilthepowersupplies
havereachedtheirnormaloperatingconditions.Notethatadevicepower-upcycleisnotrequiredto
initiateaPower-onReset.
ThefollowingsequencemustbefollowedduringaPower-onReset:
1.WaitforallpowersuppliestoreachnormaloperatingconditionswhilekeepingthePORpinasserted
(drivenlow).
WhilePORisasserted,allpinsaresettohigh-impedance.AfterthePORpinisdeasserted(driven
high),allZgrouppins,lowgrouppins,andhighgrouppinsaresettotheirresetstateandremainat
theirresetstateuntiltheotherwiseconfiguredbytheirrespectiveperipheral.Allperipherals,except
thoseselectedforbootpurposes,aredisabledafteraPower-onResetandmustbeenabledthrough
theDeviceStateControlregisters;formoredetails,seeSection3.3,PeripheralSelectionAfterDevice
Reset.
2.Onceallthepowersuppliesarewithinvalidoperatingconditions,thePORpinmustremainasserted
(low)foraminimumof256CLKIN2cycles.ThePLL1controllerinputclock,CLKIN1,andthePCIinput
clock,PCLK,mustalsobevalidduringthistime.PCLKisonlyneededifthePCImoduleisbeingused.
IftheDDR2memorycontrollerandtheEMACperipheralarenotneeded,CLKIN2canbetiedlowand,
inthiscase,thePORpinmustremainasserted(low)foraminimumof256CLKIN1cyclesafterall
powersupplieshavereachedvalidoperatingconditions.
WithinthelowperiodofthePORpin,thefollowinghappens:
–Theresetsignalsflowtotheentirechip(includingthetestandemulationlogic),resettingmodules
thatuseresetasynchronously.
–ThePLL1controllerclocksarestartedatthefrequencyofthesystemreferenceclock.Theclocks
arepropagatedthroughoutthechiptoresetmodulesthatuseresetsynchronously.Bydefault,
PLL1isinresetandunlocked.
–ThePLL2controllerclocksarestartedatthefrequencyofthesystemreferenceclock.PLL2isheld
inreset.SincethePLL2controlleralwaysoperatesinPLLmode,thesystemreferenceclockand
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