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7.6.8ResetElectricalData/Timing
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Table7-14.TimingRequirementsforReset
(1)(2)(3)
(seeFigure7-8andFigure7-9)
-720
-850
A-1000/-1000
NO.UNIT
-1200
MINMAX
5t
w(POR)
Pulseduration,PORlow256D
(4)
ns
6t
w(RESET)
Pulseduration,RESETlow24Cns
Setuptime,bootmodeandconfigurationpinsvalidbeforePORhighor
7t
su(boot)
6Pns
RESEThigh
(5)
Holdtime,bootmodeandconfigurationpinsvalidafterPORhighor
8t
h(boot)
6Pns
RESEThigh
(5)
(1)C=1/CLKIN1clockfrequencyinns.
(2)D=1/CLKIN2clockfrequencyinns.
(3)P=1/CPUclockfrequencyinnanoseconds(ns).Notethatafterpower-onreset,warmreset,andmaxresettheCPUfrequencyisequal
totheCLKIN1frequencydividedbythreeduetothePLL1controllerbeingreset(seeSection7.6,ResetController).
(4)IfCLKIN2isnotused,t
w(POR)
mustbemeasuredintermsofCLKIN1cycles;otherwise,useCLKIN2cycles.
(5)AEA[19:0],ABA[1:0],andPCI_ENarethebootconfigurationpinsduringdevicereset.Note:Ifaconfigurationpinmustberoutedout
fromthedeviceand3-stated(notdriven),theinternalpullup/pulldown(IPU/IPD)resistorshouldnotbereliedupon;TIrecommendsthe
useofanexternalpullup/pulldownresistor.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal
pullup/pulldownresistorsarerequired,seeSection3.7,Pullup/PulldownResistors.
Table7-15.SwitchingCharacteristicsOverRecommendedOperatingConditionsDuringReset
(1)
(seeFigure7-9)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
MINMAX
9t
d(PORH-RSTATH)
Delaytime,PORhighANDRESEThightoRESETSTAThigh15000Cns
(1)C=1/CLKIN1clockfrequencyinns.
ForFigure7-8,notethefollowing:
•Zgroupconsistsof:allI/O/ZandO/Zpins,exceptforLowandHighgrouppins.Pinsbecomehigh
impedanceassoonastheirrespectivepowersupplyhasreachednormaloperatingconditions.Pins
remaininhighimpedanceuntilconfiguredotherwisebytheirrespectiveperipheral.
•Lowgroupconsistsof:UXDATA0/MTXD0/RMTXD0,UXDATA1/MTXD1/RMTXD1,
UXDATA2/MTXD2/RMTXD2,UXDATA3/MTXD3/RMTXD3,UXDATA4/MTXD4/RMTXD4,and
UXENB/MTXEN/RMTXEN.Pinsbecomelowassoonastheirrespectivepowersupplyhasreached
normaloperatingconditions.Pinsremainlowuntilconfiguredotherwisebytheirrespectiveperipheral.
•Highgroupconsistsof:AHOLD,ABUSREQ,andHRDY/PIRDY.Pinsbecomehighassoonastheir
respectivepowersupplyhasreachednormaloperatingconditions.Pinsremainhighuntilconfigured
otherwisebytheirrespectiveperipheral.TheABUSREQpinremainshighuntiltheEMIFAisenabled
throughthePERCFG1register.OncetheEMIFAisenabled,theABUSREQpinisdriventoitsinactive
state(drivenlow).
•AllperipheralsmustbeenablethroughsoftwarefollowingaPower-onReset;formoredetails,see
Section7.6.1,Power-onReset.
•Forpower-supplysequencerequirements,seeSection7.3.1,Power-SupplySequencing.
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