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7.7.3PLL1ControllerRegisterDescriptions
7.7.3.1PLL1ControlRegister
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThissectionprovidesadescriptionofthePLL1controllerregisters.FordetailsontheoperationofthePLL
controllermodule,seetheTMS320C645xDSPSoftware-ProgrammablePhase-LockedLoop(PLL)
ControllerUser'sGuide(literaturenumberSPRUE56).
NOTE:ThePLL1controllerregisterscanonlybeaccessedusingtheCPUortheemulator.
NotalloftheregistersdocumentedintheTMS320C645xDSPSoftware-ProgrammablePhase-Locked
Loop(PLL)ControllerUser'sGuide(literaturenumberSPRUE56)aresupportedontheC6455.Onlythose
registersdocumentedinthissectionaresupported.Furthermore,onlythebitswithintheregisters
describedherearesupported.Youshouldnotwritetoanyreservedmemorylocationorchangethevalue
ofreservedbits.
ThePLLcontrolregister(PLLCTL)isshowninFigure7-11anddescribedinTable7-19.
3116
Reserved
R-0
15876543210
PLL
ReservedRsvdRsvdReservedPLLRSTRsvdPLLEN
PWRDN
R-0R/W-0R-1R/W-0R/W-1R-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-11.PLL1ControlRegister(PLLCTL)[HexAddress:029A0100]
Table7-19.PLL1ControlRegister(PLLCTL)FieldDescriptions
BitFieldValueDescription
31:8ReservedReserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
7ReservedReserved.Writestothisregistermustkeepthisbitas0.
6ReservedReserved.Thereservedbitlocationisalwaysreadas1.Avaluewrittentothisfieldhasnoeffect.
5:4ReservedReserved.Writestothisregistermustkeepthisbitas0.
3PLLRSTPLLresetbit
0PLLresetisreleased
1PLLresetisasserted
2ReservedReserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
1PLLPWRDNPLLpower-downmodeselectbit
0PLLisoperational
1PLLisplacedinpower-downstate,i.e.,allanalogcircuitryinthePLListurned-off
0PLLENPLLenablebit
0Bypassmode.DividerPREDIVandPLLarebypassed.Allthesystemclocks(SYSCLKn)are
divideddowndirectlyfrominputreferenceclock.
1PLLmode.DividerPREDIVandPLLarenotbypassed.PLLoutputpathisenabled.Allthesystem
clocks(SYSCLKn)aredivideddownfromPLLoutput.
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