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7.6.3MaxReset
7.6.4SystemReset
7.6.5CPUReset
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Section2.4,BootSequence).
NOTE
ThePORpinshouldbeheldinactive(high)throughouttheWarmResetsequence.
Otherwise,ifPORisactivated(broughtlow),theminimumPORpulsewidthmustbemet.
TheRESETpinshouldnotbetiedtogetherwiththePORpin.
AMaxResetisinitiatedbytheRapidIOperipheralandhasthesameaffectasaWarmReset.
TheemulatorinitiatesaSystemResetviatheICEPickmodule.ThisICEPick-initiatedresetis
non-maskable.ToinvokethemaximumresetviatheICEPickmodule,theusercanperformthefollowing
fromtheCodeComposerStudio™menu:Debug→AdvancedResets→SystemReset.
ThefollowingmemorycontentsaremaintainedduringaSystemReset:
•DDR2MemoryController:TheDDR2MemoryControllerregistersarenotreset.Inaddition,theDDR2
SDRAMmemorycontentisretainediftheuserplacestheDDR2SDRAMinself-refreshmodebefore
invokingtheSystemReset.
•EMIFA:ThecontentsofthememoryconnectedtotheEMIFAareretained.TheEMIFAregistersare
notreset.
Test,emulation,andclocklogicareunaffected.Thedeviceconfigurationpinsarealsonotre-latchedand
thestateoftheperipherals(seeTable3-4)isnotaffected.
DuringaSystemReset,thefollowinghappens:
1.TheSystemResetisinitiatedbytheemulator.
Duringthistime,thefollowinghappens:
–Theresetsignalsflowtotheentirechipresettingallthemodulesonchipexceptthetestand
emulationlogic.
–ThePLLcontrollersarenotreset.Internalsystemclocksareunaffected.IfPLL1/PLL2werelocked
beforetheSystemReset,theyremainlocked.
–TheRESETSTATpingoeslowtoindicateaninternalresetisbeinggenerated.
2.Afterdeviceinitializationiscomplete,theRESETSTATpinisdeasserted(drivenhigh).Inaddition,the
PLLcontrollerspausetheirsystemclocksforabout10cycles.
Atthispoint:
–ThestateoftheperipheralsbeforetheSystemResetisnotchanged.Forexample,ifMcBSP0was
intheenabledstatebeforeSystemReset,itwillremainintheenabledstateafterSystemReset.
–TheI/OpinsarecontrolledasdictatedbytheDEVSTATregister.
–TheDDR2MemoryControllerandEMIFAregistersretaintheirpreviousvalues.OnlytheDDR2
MemoryControllerandEMIFAstatemachinesareresetbytheSystemReset.
–ThePLLcontrollersareoperatinginthemodepriortoSystemReset.Systemclocksare
unaffected.
Thebootsequenceisstartedafterthesystemclocksarerestarted.Sincetheconfigurationpins(including
theBOOTMODE[3:0]pins)arenotlatchedwithaSystemReset,thepreviousvalues,asshowninthe
DEVSTATregister,areusedtoselectthebootmode.
ACPUResetisinitiatedbytheHPIorPCIperipheral.ThisresetonlyaffectstheCPU.Duringa
PCI-initiatedCPUReset,thePCIpinsaresettotheirresetstate.WiththeexceptionoftheHRDY/PIRDY
pin,thePCIpinshavearesetstateofhigh-impedance;theHRDY/PIRDYpingoeshighduringreset.
C64x+PeripheralInformationandElectricalSpecifications 130SubmitDocumentationFeedback