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7.14.3.2EMACRMIIElectricalData/Timing
RMREFCLK
(Input)
1
2
3
3
1
RMREFCLK
(Input)
MTXD1-MTXD0,
MTXEN (Outputs)
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
TheRMREFCLKpinisusedtosourceaclocktotheEMACwhenitisconfiguredforRMIIoperation.The
RMREFCLKfrequencyshouldbe50MHz±50PPMwithadutycyclebetween35%and65%,inclusive.
Table7-81.TimingRequirementsforRMREFCLK-RMIIOperation(seeFigure7-65)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
MINMAX
1t
w(RMREFCLKH)
Pulseduration,RMREFCLKhigh713ns
2t
w(RMREFCLKL)
Pulseduration,RMREFCLKlow713ns
3t
t(RMREFCLK)
Transitiontime,RMREFCLK2ns
Figure7-65.RMREFCLKTiming
Table7-82.SwitchingCharacteristicsOverRecommendedOperatingConditionsforEMACRMIITransmit
10/100Mbit/s
(1)
(seeFigure7-66)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
1000Mbps
MINMAX
1t
d(RMREFCLKH-MTXD)
Delaytime,RMREFCLKhightotransmitselectedsignalsvalid310ns
(1)ForRMII,transmitselectedsignalsinclude:MTXD[1:0]andMTXEN.
Figure7-66.EMACTransmitInterfaceTiming[RMIIOperation]
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