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7.7PLL1andPLL1Controller
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
TheprimaryPLLcontrollergeneratestheinputclocktotheC64x+megamodule(includingtheCPU)as
wellasmostofthesystemperipheralssuchasthemultichannelbufferedserialports(McBSPs)andthe
externalmemoryinterface(EMIF).
AsshowninFigure7-10,thePLL1controllerfeaturesasoftware-programmablePLLmultipliercontroller
(PLLM)andfivedividers(PREDIV,D2,D3,D4,andD5).ThePLL1controllerusesthedeviceinputclock
CLKIN1togenerateasystemreferenceclock(SYSREFCLK)andfoursystemclocks(SYSCLK2,
SYSCLK3,SYSCLK4,andSYSCLK5).
PLL1powerissuppliedexternallyviathePLL1power-supplypin(PLLV1).AnexternalEMIfiltercircuit
mustbeaddedtoPLLV1,asshowninFigure7-10.The1.8-VsupplyoftheEMIfiltermustbefromthe
same1.8-VpowerplanesupplyingtheI/Opower-supplypin,DV
DD18
.TIrequiresEMIfiltermanufacturer
Murata,partnumberNFM18CC222R1C3orNFM18CC223R1C3.
AllPLLexternalcomponents(C1,C2,andtheEMIFilter)mustbeplacedasclosetotheC64x+DSP
deviceaspossible.Forthebestperformance,TIrecommendsthatallthePLLexternalcomponentsbeon
asinglesideoftheboardwithoutjumpers,switches,orcomponentsotherthantheonesshown.For
reducedPLLjitter,maximizethespacingbetweenswitchingsignalsandthePLLexternalcomponents
(C1,C2,andtheEMIFilter).
TheminimumCLKIN1riseandfalltimesshouldalsobeobserved.Fortheinputclocktiming
requirements,seeSection7.7.4,PLL1ControllerInputandOutputClockElectricalData/Timing.
CAUTION
ThePLLcontrollermoduleasdescribedintheTMS320C645xDSP
Software-ProgrammablePhase-LockedLoop(PLL)ControllerUser'sGuide(literature
numberSPRUE56)includesasupersetoffeatures,someofwhicharenotsupported
ontheC6455DSP.Thefollowingsectionsdescribethefeaturesthataresupported;it
shouldbeassumedthatanyfeaturenotincludedinthesesectionsisnotsupported
bytheC6455DSP.
C64x+PeripheralInformationandElectricalSpecifications 136SubmitDocumentationFeedback