Filter
Top Products
www.ti.com
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
softwaresuchasCodeComposerStudio.
ForthePCIhostboot,theCPUisoutofreset,butitexecutesanIDLEinstructionuntilaDSPinterrupt
isgeneratedbythehost.ThehostcangenerateaDSPinterruptthroughthePCIperipheralbysetting
theDSPINTbitintheBack-EndApplicationInterruptEnableSetRegister(PCIBINTSET)andthe
StatusSetRegister(PCISTATSET).
NotethattheHPIhostbootisahardwarebootmodewhilethePCIhostbootisasoftwarebootmode.
IfPCIbootisselected,theon-chipbootloaderconfiguresthePLL1ControllersuchthatCLKIN1is
multipliedby15.Morespecifically,PLLMissetto0Eh(x15)andRATIOissetto0(÷1)inthePLL1
MultiplierControlRegister(PLLM)andPLL1Pre-DividerRegister(PREDIV),respectively.TheCLKIN1
frequencymustnotbegreaterthan50MHzsothatthemaximumspeedoftheinternalROM,750
MHz,isnotviolated.TheCFGGP[2:0]pinsmustbesetto000bduringresetforproperoperationofthe
PCIbootmode.
Asmentionedpreviously,aDSPinterruptmustbegeneratedattheendofthehostbootprocessto
beginexecutionoftheloadedapplication.BecausetheDSPinterruptgeneratedbytheHPIandPCIis
mappedtotheEDMAeventDSP_EVT(DMAchannel0),itwillgetrecordedinbit0oftheEDMA
EventRegister(ER).ThiseventmustbeclearedbysoftwarebeforetriggeringtransfersonDMA
channel0.
•EMIFA8bitROMboot(BOOTMODE[3:0]=0100b)
Afterreset,thedevicewillbeginexecutingsoftwareoutofanAsynchronous8bitROMlocatedin
EMIFACE3spaceusingthedefaultsettingsintheEMIFAregisters.Thisbootmodeisahardware
bootmode.
•MasterI2Cboot(BOOTMODE[3:0]=0101b)
Afterreset,theDSPcanactasamastertotheI2CbusandcopydatafromanI2CEEPROMora
deviceactingasanI2CslavetotheDSPusingapredefinedboottableformat.Thedestination
addressandlengtharecontainedwithintheboottable.Thisbootmodeisasoftwarebootmode.
•SlaveI2Cboot(BOOTMODE[3:0]=0110b)
ASlaveI2Cbootisalsoimplemented,whichprogramstheDSPasanI2CSlaveandsimplywaitsfora
Mastertosenddatausingastandardboottableformat.
UsingtheSlaveI2Cboot,asingleDSPoradeviceactingasanI2CMastercansimultaneouslyboot
multipleslaveDSPsconnectedtothesameI2Cbus.NotethattheMasterDSPmayrequirebooting
viaanI2CEEPROMbeforeactingasaMasterandbootingotherDSPs.
TheSlaveI2Cbootisasoftwarebootmode.
•SerialRapidIOboot(BOOTMODE[3:0]=1000bthrough1111b)
Afterreset,thefollowingsequenceofeventsoccur:
–Theon-chipbootloaderconfiguresdeviceregisters,includingSerDes,andEDMA3
–Theon-chipbootloaderresetstheperipheral'sstatemachinesandregisters
–RapidIOportssendidlecontrolsymbolstoinitializeSerDesports
–ThehostexploresthesystemwithRapidIOmaintenancepackets
–Thehostidentifies,enumerates,andinitializestheRapidIOdevice
–ThehostcontrollerconfiguresDSPperipheralsthroughmaintenancepackets
–TheapplicationsoftwareissentfromthehostcontrollertoDSPmemory
–TheDSPCPUisawakenedbyinterruptsuchasaRapidIODOORBELLpacket
–Theapplicationsoftwareisexecutedandnormaloperationfollows
ForSerialRapidIOboot,BOOTMODE2(L26pin)isusedinconjunctionwithCFGGP[2:0](T26,U26,
andU25pins,respectively)todeterminethedeviceaddresswithintheRapidIOnetwork.
BOOTMODE2istheMSBoftheaddress,whileCFGGP[2:0]areusedasthethreeLSBs–givingthe
usertheopportunitytohaveupto16uniquedeviceIDs.
BOOTMODE[1:0](L25andP26,respectively)denotetheconfigurationoftheRapidIOperipheral;i.e.,
"00b"referstoRapidIOConfiguration0.ForexactdeviceRapidIOConfigurations,seethe
TMS320C645xxBootloaderUser'sGuide(literaturenumberSPRUEC6).
DeviceOverview 18SubmitDocumentationFeedback