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7.7.3.8PLLControllerClockAlignControlRegister
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePLLcontrollerclockaligncontrolregister(ALNCTL)isshowninFigure7-18anddescribedin
Table7-26.
3116
Reserved
R-0
1554320
ReservedALN5ALN4Reserved
R-0R-1R-1R-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-18.PLLControllerClockAlignControlRegister(ALNCTL)[HexAddress:029A0140]
Table7-26.PLLControllerClockAlignControlRegister(ALNCTL)FieldDescriptions
BitFieldValueDescription
31:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4:3ALNnSYSCLKnalignment.Donotchangethedefaultvaluesofthesefields.
0DonotalignSYSCLKntootherSYSCLKsduringGOoperation.IfSYSninDCHANGEissetto1,
SYSCLKnswitchestothenewratioimmediatelyaftertheGOSETbitinPLLCMDisset.
1AlignSYSCLKntootherSYSCLKsselectedinALNCTLwhentheGOSETbitinPLLCMDisset.
TheSYSCLKnratioissettotheratioprogrammedintheRATIObitinPLLDIVn.
2:0Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
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