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7.16EnhancedViterbi-DecoderCoprocessor(VCP2)
7.16.1VCP2Device-SpecificInformation
7.16.2VCP2PeripheralRegisterDescription(s)
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
TheC6455devicehasahigh-performanceembeddedcoprocessor[Viterbi-DecoderCoprocessor(VCP2)
thatsignificantlyspeedsupchannel-decodingoperationson-chip.TheVCP2operatingatCPUclock
divided-by-4candecodeover6947.95-Kbpsadaptivemulti-rate(AMR)[K=9,R=1/3]voicechannels.
TheVCP2supportsconstraintlengthsK=5,6,7,8,and9,ratesR=3/4,1/2,1/3,1/4,and1/5,and
flexiblepolynomials,whilegeneratingharddecisionsorsoftdecisions.Communicationsbetweenthe
VCP2andtheCPUarecarriedoutthroughtheEDMA3controller.
TheVCP2supports:
•Unlimitedframesizes
•Coderates3/4,1/2,1/3,1/4,and1/5
•Constraintlengths5,6,7,8,and9
•Programmableencoderpolynomials
•Programmablereliabilityandconvergencelengths
•Hardandsoftdecodeddecisions
•Tailandconvergentmodes
•Yamamotologic
•Tailbitinglogic
•VariousinputandoutputFIFOlengths
FormoredetailedinformationontheVCP2,seetheTMS320C645xDSPViterbi-DecoderCoprocessor2
(VCP2)ReferenceGuide(literaturenumberSPRU972).
Table7-96.VCP2Registers
EDMABUSCONFIGURATIONBUS
ACRONYMREGISTERNAME
HEXADDRESSRANGEHEXADDRESSRANGE
58000000-VCPIC0VCP2InputConfigurationRegister0
58000004-VCPIC1VCP2InputConfigurationRegister1
58000008-VCPIC2VCP2InputConfigurationRegister2
5800000C-VCPIC3VCP2InputConfigurationRegister3
58000010-VCPIC4VCP2InputConfigurationRegister4
58000014-VCPIC5VCP2InputConfigurationRegister5
58000018-58000044-Reserved
58000048-VCPOUT0VCP2OutputRegister0
5800004C-VCPOUT1VCP2OutputRegister1
58000050-5800007C-Reserved
58000080N/AVCPWBMVCP2BranchMetricsWriteFIFORegister
58000084-5800009C-Reserved
580000C0N/AVCPRDECSVCP2DecisionsReadFIFORegister
N/A02B80018VCPEXEVCP2ExecutionRegister
N/A02B80020VCPENDVCP2EndianModeRegister
N/A02B80040VCPSTAT0VCP2StatusRegister0
N/A02B80044VCPSTAT1VCP2StatusRegister1
N/A02B80050VCPERRVCP2ErrorRegister
-Reserved
N/A02B80060VCPEMUVCP2EmulationControlRegister
N/A02B80064-02B9FFFF-Reserved
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