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7.9DDR2MemoryController
7.9.1DDR2MemoryControllerDevice-SpecificInformation
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
The32bit,533-MHz(datarate)DDR2MemoryControllerbusoftheC6455isusedtointerfaceto
JESD79D-2Astandard-compliantDDR2SDRAMdevices.TheDDR2externalbusonlyinterfacestoDDR2
SDRAMdevices(upto512MB);itdoesnotsharethebuswithanyothertypesofperipherals.The
decouplingofDDR2memoriesfromotherdevicesbothsimplifiesboarddesignandprovidesI/O
concurrencyfromasecondexternalmemoryinterface,EMIFA.
TheinternaldatabusclockfrequencyandDDR2busclockfrequencydirectlyaffectthemaximum
throughputoftheDDR2bus.TheclockfrequencyoftheDDR2busisequaltotheCLKIN2frequency
multipliedby10.TheinternaldatabusclockfrequencyoftheDDR2MemoryControllerisfixedata
divide-by-threeratiooftheCPUfrequency.ThemaximumDDR2throughputisdeterminedbythesmaller
ofthetwobusfrequencies.Forexample,iftheinternaldatabusfrequencyis333MHz(CPUfrequencyis
1GHz)andtheDDR2busfrequencyis267MHz(CLKIN2frequencyis26.7MHz),themaximumdata
rateachievablebytheDDR2memorycontrolleris2.1Gbytes/sec.TheDDR2busisdesignedtosustaina
maximumthroughputofupto2.1Gbytes/secata533-MHzdatarate(267-MHzclockrate),aslongas
datarequestsarependingintheDDR2MemoryController.
TheapproachtospecifyinginterfacetimingfortheDDR2memorybusisdifferentthanonotherinterfaces
suchasEMIF,HPI,andMcBSP.Fortheseotherinterfacesthedevicetimingwasspecifiedintermsof
datamanualspecificationsandI/Obufferinformationspecification(IBIS)models.
FortheC6455DDR2memorybus,theapproachistospecifycompatibleDDR2devicesandprovidethe
printedcircuitboard(PCB)solutionandguidelinesdirectlytotheuser.TexasInstruments(TI)has
performedthesimulationandsystemcharacterizationtoensureallDDR2interfacetimingsinthissolution
aremet.ThecompleteDDR2systemsolutionisdocumentedintheImplementingDDR2PCBLayouton
theTMS320C6455applicationreport(literaturenumberSPRAAA7).
TIonlysupportsdesignsthatfollowtheboarddesignguidelinesoutlinedintheSPRAAA7
applicationreport.
TheDDR2MemoryControllerpinsmustbeenabledbysettingtheDDR2_ENconfigurationpin(ABA0)
highduringdevicereset.Formoredetails,seeSection3.1,DeviceConfigurationatDeviceReset.
TheODT[1:0]pinsofthememorycontrollermustbeleftunconnected.TheODTpinsontheDDR2
memorydevice(s)mustbeconnectedtoground.
TheDDR2memorycontrollerontheC6455devicesupportsthefollowingmemorytopologies:
•A32bitwideconfigurationinterfacingtotwo16bitwideDDR2SDRAMdevices.
•A16bitwideconfigurationinterfacingtoasingle16bitwideDDR2SDRAMdevice.
AraceconditionmayexistwhencertainmasterswritedatatotheDDR2memorycontroller.Forexample,
ifmasterApassesasoftwaremessageviaabufferinexternalmemoryanddoesnotwaitforindication
thatthewritecompletes,whenmasterBattemptstoreadthesoftwaremessage,thenthemasterBread
maybypassthemasterAwriteand,thus,masterBmayreadstaledataand,therefore,receivean
incorrectmessage.
Somemasterperipherals(e.g.,EDMA3transfercontrollers)willalwayswaitforthewritetocomplete
beforesignalinganinterrupttothesystem,thusavoidingthisracecondition.Formastersthatdonothave
hardwareguaranteeofwrite-readordering,itmaybenecessarytoguaranteedataorderingviasoftware.
IfmasterAdoesnotwaitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround:
1.Performtherequiredwrite.
2.PerformadummywritetotheDDR2memorycontrollermoduleIDandrevisionregister.
3.PerformadummyreadtotheDDR2memorycontrollermoduleIDandrevisionregister.
4.IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The
completionofthereadinstep3ensuresthatthepreviouswritewasdone.
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