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SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
InterfaceModeClocking
Theon-chipPLL2andPLL2ControllergeneratetheclockstotheEMACmoduleinRGMIIorGMIImode.
WhentheEMACisenabledwiththesemodes,theinputclocktothePLL2Controller(CLKIN2)musthave
a25-MHzfrequency.Formoreinformation,seeSection7.8,PLL2andPLL2Controller.
TheEMACusesSYSCLK1ofthePLL2ControllertogeneratethenecessaryclocksfortheGMIIand
RGMIImodes.Whenthesemodesareused,thefrequencyofCLKIN2mustbe25MHz.Also,dividerD1
shouldbeprogrammedto÷2mode[default]whenusingtheGMIImodeandto÷5modewhenusingthe
RGMIImode.DividerD1issoftwareprogrammableand,ifnecessary,mustbeprogrammedafterdevice
resetto÷5whentheRGMIImodeoftheEMACisused.
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