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7.7.3.5PLLControllerDivider5Register
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePLLcontrollerdivider5register(PLLDIV5)isshowninFigure7-15anddescribedinTable7-23.
3116
Reserved
R-0
1514540
D5ENReservedRATIO
R/W-1R-0R/W-3
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-15.PLLControllerDivider5Register(PLLDIV5)[HexAddress:029A0164]
Table7-23.PLLControllerDivider5Register(PLLDIV5)FieldDescriptions
BitFieldValueDescription
31:16Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
15Dn4ENDivider4enablebit.
0Divider4isdisabled.Noclockoutput.
1Divider4isenabled.
14:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4:0RATIO0-1FhDividerratiobits.
0÷1.Dividefrequencyby1.
1h÷2.Dividefrequencyby2.
2h÷3.Dividefrequencyby3.
3h÷4.Dividefrequencyby4.
4h-7h÷5to÷8.Dividefrequencyby5todividefrequencyby8.
8h-1FhReserved,donotuse.
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