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2.4BootSequence
2.4.1BootModesSupported
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThebootsequenceisaprocessbywhichtheDSP'sinternalmemoryisloadedwithprogramanddata
sectionsandtheDSP'sinternalregistersareprogrammedwithpredeterminedvalues.Thebootsequence
isstartedautomaticallyaftereachpower-onreset,warmreset,maxreset,andsystemreset.Formore
detailsontheinitiatorsoftheseresets,seeSection7.6,ResetController.
Thereareseveralmethodsbywhichthememoryandregisterinitializationcantakeplace.Eachofthese
methodsisreferredtoasabootmode.Thebootmodetobeusedisselectedatresetthroughthe
BOOTMODE[3:0]pins.
Eachbootmodecanbeclassifiedasahardwarebootmodeorasasoftwarebootmode.Softwareboot
modesrequiretheuseoftheon-chipbootloader.ThebootloaderisDSPcodethattransfersapplication
codefromanexternalsourceintointernalorexternalprogrammemoryaftertheDSPistakenoutofreset.
ThebootloaderispermanentlystoredintheinternalROMoftheDSPstartingatbyteaddress0010
0000h.Hardwarebootmodesarecarriedoutbythebootconfigurationlogic.Thebootconfigurationlogic
isactualhardwarethatdoesnotrequiretheexecutionofDSPcode.Section2.4.1,BootModes
Supported,describeseachbootmodeinmoredetail.
WhenaccessingtheinternalROMoftheDSP,theCPUfrequencymustalwaysbelessthan750MHz.
Therefore,whenusingasoftwarebootmode,caremustbetakensuchthattheCPUfrequencydoesnot
exceed750MHzatanypointduringthebootsequence.Afterthebootsequencehascompleted,theCPU
frequencycanbeprogrammedtothefrequencyrequiredbytheapplication.
TheC6455hassixbootmodes:
•Noboot(BOOTMODE[3:0]=0000b)
Withnoboot,theCPUexecutesdirectlyfromtheinternalL2SRAMlocatedataddress0x800000.
Note:deviceoperationsareundefinedifinvalidcodeislocatedataddress0x800000.Thisbootmode
isahardwarebootmode.
•Hostboot(BOOTMODE[3:0]=0001bandBOOTMODE[3:0]=0111b)
Ifhostbootisselected,afterreset,theCPUisinternally"stalled"whiletheremainderofthedeviceis
released.Duringthisperiod,anexternalhostcaninitializetheCPU'smemoryspaceasnecessary
throughHostPortInterface(HPI)orthePeripheralComponentInterconnect(PCI)interface.Internal
configurationregisters,suchasthosethatcontroltheEMIFalsocanbeinitializedbythehostwithtwo
exceptions:DeviceStateControlregisters(Section3.4),PLL1andPLL2Controllerregisters
(Section7.7andSection7.8)cannotbeaccessedthroughanyhostinterface,includingHPIandPCI.
Oncethehostisfinishedwithallnecessaryinitialization,itmustgenerateaDSPinterrupt(DSPINT)to
completethebootprocess.ThistransitioncausesbootconfigurationlogictobringtheCPUoutofthe
"stalled"state.TheCPUthenbeginsexecutionfromtheinternalL2SRAMlocatedat0x800000.Note
thattheDSPinterruptisregisteredinbit0(channel0)oftheEDMAEventRegister(ER).Thisevent
mustbeclearedbysoftwarebeforetriggeringtransfersonDMAchannel0.
Allmemory,withtheexceptionspreviouslydescribed,maybewrittentoandreadbythehost.This
allowsforthehosttoverifywhatitsendstotheDSPifrequired.AftertheCPUisoutofthe"stalled"
state,theCPUneedstocleartheDSPINT,otherwise,nomoreDSPINTscanbereceived.
Aspreviouslymentioned,fortheC6455device,theHostPortInterface(HPI)andthePeripheral
ComponentInterconnect(PCI)interfacecanbeusedforhostboot.TousetheHPIforhostboot,the
PCI_ENpin(Y29)mustbelow[default](enablingtheHPIperipheral)andBOOTMODE[3:0]mustbe
setto0001batdevicereset.Conversely,tousethePCIinterfaceforhostboot,thePCI_ENpin(Y29)
mustbehigh(enablingthePCIperipheral)andBOOTMODE[3:0]mustbesetto0111batdevicereset.
FortheHPIhostboot,theDSPinterruptcanbegeneratedthroughtheuseoftheDSPINTbitinthe
HPIControl(HPIC)register.
FortheHPIhostboot,theCPUisactuallyheldinresetuntilaDSPinterruptisgeneratedbythehost.
TheDSPinterruptcanbegeneratedthroughtheuseoftheDSPINTbitintheHPIControl(HPIC)
register.BecausetheCPUisheldinresetduringHPIhostboot,itdoesnotrespondtoemulation
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