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7.10.4HOLD/HOLDATiming
HOLD
HOLDA
EMIF Bus
(A)
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
DSP DSP
1
3
2 5
4
AECLKOUT
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Table7-48.TimingRequirementsfortheHOLD/HOLDACyclesforEMIFAModule
(1)
(seeFigure7-39)
-720
-850
A-1000/-1000
NO.UNIT
-1200
MINMAX
3t
h(HOLDAL-HOLDL)
Holdtime,HOLDlowafterHOLDAlowEns
(1)E=theEMIFinputclock(ECLKIN)periodinnsforEMIFA.
Table7-49.SwitchingCharacteristicsOverRecommendedOperatingConditionsfortheHOLD/HOLDA
CyclesforEMIFAModule
(1)(2)
(seeFigure7-39)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
MINMAX
1t
d(HOLDL-EMHZ)
Delaytime,HOLDlowtoEMIFABushighimpedance2E
(3)
ns
2t
d(EMHZ-HOLDAL)
Delaytime,EMIFBushighimpedancetoHOLDAlow02Ens
4t
d(HOLDH-EMLZ)
Delaytime,HOLDhightoEMIFBuslowimpedance2E7Ens
5t
d(EMLZ-HOLDAH)
Delaytime,EMIFABuslowimpedancetoHOLDAhigh02Ens
(1)E=theEMIFinputclock(ECLKIN)periodinnsforEMIFA.
(2)EMIFABusconsistsof:ACE[5:2],ABE[7:0],AED[63:0],AEA[19:0],ABA[1:0],AR/W,ASADS/ASRE,AAOE/ASOE,andAAWE/ASWE.
(3)AllpendingEMIFtransactionsareallowedtocompletebeforeHOLDAisasserted.Ifnobustransactionsareoccurring,thenthe
minimumdelaytimecanbeachieved.
A.EMIFABusconsistsof:ACE[5:2],ABE[7:0],AED[63:0],AEA[19:0],ABA[1:0],AR/W,ASADS/ASRE,AAOE/ASOE,
andAAWE/ASWE.
Figure7-39.HOLD/HOLDATimingforEMIFA
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