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3.4.3PeripheralConfigurationRegister1Description
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePeripheralConfigurationRegister(PERCFG1)isusedtoenabletheEMIFAandDDR2Memory
Controller.EMIFAandtheDDR2MemoryControllerdonothavecorrespondingstatusbitsinthe
PeripheralStatusRegisters.TheEMIFAandDDR2MemoryControllerperipheralscanbeusedwithin16
SYSCLK3cyclesafterEMIFACTLandDDR2CTLaresetto1.OnceEMIFACTLandDDR2CTLaresetto
1,theycannotbesetto0.NotethatiftheDDR2MemoryControllerandEMIFAaredisabledatreset
throughthedeviceconfigurationpins(DDR2.EN[ABA0]andEMIFA[ABA1]),theycannotbeenabled
throughthePERCFG1register.
318
Reserved
R-0x00
7210
ReservedDDR2CTLEMIFACTL
R-0x00R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure3-5.PeripheralConfigurationRegister1(PERCFG1)-0x02AC002C
Table3-8.PeripheralConfigurationRegister1(PERCFG1)FieldDescriptions
BitFieldValueDescription
31:2ReservedReserved.
1DDR2CTLModeControlforDDR2MemoryController.Oncethisbitissetto1,itcannotbechangedto0.
0SetDDR2todisabled
1SetDDR2toenabled
0EMIFACTLModecontrolforEMIFA.Oncethisbitissetto1,itcannotbechangedto0.Thisbitdefaultsto1if
EMIFA8bitROMbootisused(BOOTMODE[3:0]=0100b).
0SetEMIFAtodisabled
1SetEMIFAtoenabled
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