Filter
Top Products
www.ti.com
7.22.3IEEE1149.1JTAG
7.22.3.1JTAGDevice-SpecificInformation
7.22.4JTAGPeripheralRegisterDescription(s)
7.22.5JTAGElectricalData/Timing
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
7.22.3.1.1IEEE1149.1JTAGCompatibilityStatement
Formaximumreliability,theC6455DSPincludesaninternalpulldown(IPD)ontheTRSTpintoensure
thatTRSTwillalwaysbeasserteduponpowerupandtheDSP'sinternalemulationlogicwillalwaysbe
properlyinitializedwhenthispinisnotroutedout.JTAGcontrollersfromTexasInstrumentsactivelydrive
TRSThigh.However,somethird-partyJTAGcontrollersmaynotdriveTRSThighbutexpecttheuseof
anexternalpullupresistoronTRST.WhenusingthistypeofJTAGcontroller,assertTRSTtoinitializethe
DSPafterpowerupandexternallydriveTRSThighbeforeattemptinganyemulationorboundaryscan
operations.
Table7-116.TimingRequirementsforJTAGTestPort(seeFigure7-79)
-720
-850
A-1000/-1000
NO.UNIT
-1200
MINMAX
1t
c(TCK)
Cycletime,TCK35ns
3t
su(TDIV-TCKH)
Setuptime,TDI/TMS/TRSTvalidbeforeTCKhigh10ns
4t
h(TCKH-TDIV)
Holdtime,TDI/TMS/TRSTvalidafterTCKhigh9ns
Table7-117.SwitchingCharacteristicsOverRecommendedOperatingConditionsforJTAGTestPort
(seeFigure7-79)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
MINMAX
2t
d(TCKL-TDOV)
Delaytime,TCKlowtoTDOvalid-318ns
Figure7-79.JTAGTest-PortTiming
SubmitDocumentationFeedbackC64x+PeripheralInformationandElectricalSpecifications249