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1Features
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Parameters
•ControlledBaseline
•Endianess:LittleEndian,BigEndian
–OneAssemblySite
–TestSite
•64BitExternalMemoryInterface(EMIFA)
–OneFabricationSite
–GluelessInterfacetoAsynchronous
Memories(SRAM,Flash,andEEPROM)and
•EnhancedDiminishingManufacturingSources
SynchronousMemories(SBSRAM,ZBT
(DMS)Support
SRAM)
•EnhancedProduct-ChangeNotification
–SupportsInterfacetoStandardSync
•QualificationPedigree
(1)
DevicesandCustomLogic(FPGA,CPLD,
ASICs,etc.)
•High-PerformanceFixed-PointDSP(C6455)
–32MByteTotalAddressableExternal
–1.39ns,1.17ns,1ns,and0.83ns
MemorySpace
InstructionCycleTime
•Four1xSerialRapidIO®Links(orOne4x),
–1GHzClockRate
v1.2Compliant
–Eight32BitInstructions/Cycle
–1.25/2.5/3.125GbpsLinkRates
–9600MIPS/MMACS(16Bits)
–MessagePassing,DirectIOSupport,Error
–CommercialTemperature(0°Cto90°C)
ManagementExtensions,andCongestion
–ExtendedTemperature(–40°Cto105°C)
Control
–S-Temp(–55°Cto105°C)
–IEEE1149.6CompliantI/Os
•C64x+™DSPCore
•DDR2MemoryController
–DedicatedSPLOOPInstruction
–InterfacestoDDR2-533SDRAM
–CompactInstructions(16Bit)
–32Bit/16Bit,533MHz(datarate)Bus
–InstructionSetEnhancements
–512MByteTotalAddressableExternal
–ExceptionHandling
MemorySpace
•C64x+MegamoduleL1/L2Memory
•EDMA3Controller(64IndependentChannels)
Architecture:
•32/16BitHost-PortInterface(HPI)
–256KBit(32KByte)L1PProgramCache
•32Bit33/66MHz,3.3VPeripheralComponent
(DirectMapped)
Interconnect(PCI)Master/SlaveInterface
–256KBit(32KByte)L1DDataCache
ConformstoPCILocalBusSpecification
[2-WaySet-Associative]
(version2.3)
–16MBit(2096KByte)L2UnifiedMapped
RAM/Cache(FlexibleAllocation)
•OneInter-IntegratedCircuit(I
2
C)Bus
–256KBit(32KByte)L2ROM
•TwoMcBSPs
–TimeStampCounter
•10/100/1000Mb/sEthernetMAC(EMAC)
•EnhancedVCP2
–IEEE802.3Compliant
–SupportsOver6947.95KbpsAMR
–SupportsMultipleMediaIndependent
–ProgrammableCodeParameters
Interfaces(MII,GMII,RMII,andRGMII)
–EightIndependentTransmit(TX)and
•EnhancedTurboDecoderCoprocessor(TCP2)
EightIndependentReceive(RX)Channels
–SupportsuptoEight2Mbps3GPP
(6Iterations)
•Two64BitGeneral-PurposeTimers,
–ProgrammableTurboCodeandDecodingConfigurableasFour32BitTimers
•UTOPIA
(1)ComponentqualificationinaccordancewithJEDECand
industrystandardstoensurereliableoperationoveran
–UTOPIALevel2SlaveATMController
extendedtemperaturerange.Thisincludes,butisnotlimited
–8BitTransmitandReceiveOperationsup
to,HighlyAcceleratedStressTest(HAST)orbiased85/85,
to50MHzperDirection
temperaturecycle,autoclaveorunbiasedHAST,
electromigration,bondintermetalliclife,andmoldcompound
–User-DefinedCellFormatupto64Bytes
life.Suchqualificationtestingshouldnotbeviewedas
•16General-PurposeI/O(GPIO)Pins
justifyinguseofthiscomponentbeyondspecified
performanceandenvironmentallimits.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdocument.
C64x+,JTAG,C64x+,VelociTI,C6000,CodeComposerStudio,DSP/BIOS,XDSaretrademarksofTexasInstruments.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright©2007–2008,TexasInstrumentsIncorporated
ProductsconformtospecificationsperthetermsoftheTexas
Instrumentsstandardwarranty.Productionprocessingdoesnot
necessarilyincludetestingofallparameters.