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RMREFCLK
(Input)
1
2
3
3
4
5
MRXD1-MRXD0,
MCRSDV,
MRXER (Inputs)
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Table7-83.TimingRequirementsforEMACRMIIInputReceivefor100Mbps
(1)
(seeFigure7-67)
-720
-850
A-1000/-1000
NO.UNIT
-1200
MINMAX
Setuptime,receiveselectedsignalsvalidbeforeMREFCLK(atDSP)
1t
su(MRXD-MREFCLK)
4.0ns
high/low
2t
h(MREFCLK-MRXD)
Holdtime,receiveselectedsignalsvalidafterMREFCLK(atDSP)high/low2.0ns
(1)ForRMII,receiveselectedsignalsinclude:MRXD[1:0],MRXER,andMCRSDV.
Figure7-67.EMACReceiveInterfaceTiming[RMIIOperation]
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