Texas Instruments SM320C6455-EP Personal Computer User Manual


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7.8PLL2andPLL2Controller
PLLV2
PLL2
SYSCLK2(FromPLL1Controller)
SYSCLK1
DDR2
Memory
Controller
EMAC
CLKIN2
(B)(C)
C162
560 pF
EMIFilter
+1.8V
C161
0.1 Fm
PLL2Controller
TMS320C6455DSP
PLLM
x20
/2
1
0
/x
(A)
1
SYSREFCLK
SYSCLK3(FromPLL1Controller)
PLLREF PLLOUT
DIVIDERD1
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThesecondaryPLLcontrollergeneratesinterfaceclocksfortheEthernetmediaaccesscontroller(EMAC)
andtheDDR2memorycontroller.
AsshowninFigure7-23,thePLL2controllerfeaturesaPLLmultipliercontrollerandonedivider(D1).The
PLLmultiplierisfixedtoax20multiplierrateandthedividerD1canbeprogrammedtoa÷2or÷5mode.
PLL2powerissuppliedexternallyviathePLL2powersupply(PLLV2).AnexternalPLLfiltercircuitmust
beaddedtoPLLV2asshowninFigure7-23.The1.8-VsupplyfortheEMIfiltermustbefromthesame
1.8-VpowerplanesupplyingtheI/Opower-supplypin,DV
DD18
.TIrequiresEMIfiltermanufacturerMurata,
partnumberNFM18CC222R1C3orNFM18CC223R1C3.
AllPLLexternalcomponents(C161,C162,andtheEMIFilter)shouldbeplacedasclosetotheC64x+
DSPdeviceaspossible.Forthebestperformance,TIrequiresthatallthePLLexternalcomponentsbeon
asinglesideoftheboardwithoutjumpers,switches,orcomponentsotherthantheonesshown.For
reducedPLLjitter,maximizethespacingbetweenswitchingsignalsandthePLLexternalcomponents
(C161,C162,andtheEMIFilter).TheminimumCLKIN2riseandfalltimesshouldalsobeobserved.For
theinputclocktimingrequirements,seeSection7.8.4,PLL2ControllerInputClockElectricalData/Timing.
CAUTION
ThePLLcontrollermoduleasdescribedintheTMS320C645xDSP
Software-ProgrammablePhase-LockedLoop(PLL)ControllerUser'sGuide(literature
numberSPRUE56)includesasupersetoffeatures,someofwhicharenotsupported
ontheC6455DSP.Thefollowingsectionsdescribethefeaturesthataresupported;it
shouldbeassumedthatanyfeaturenotincludedinthesesectionsisnotsupported
bytheC6455DSP.
A./xmustbeprogrammedto/2forGMII(default)andto/5forRGMII.
B.IfEMACisenabledwithRGMII,orGMII,CLKIN2frequencymustbe25MHz.
C.CLKIN2isa3.3-Vsignal.
Figure7-23.PLL2BlockDiagram
SubmitDocumentationFeedbackC64x+PeripheralInformationandElectricalSpecifications151
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