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7.7.3.9PLLDIVRatioChangeStatusRegister
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
WheneveradifferentratioiswrittentothePLLDIVnregisters,thePLLCTRLflagsthechangeinthe
PLLDIVratiochangestatusregisters(DCHANGE).DuringtheGOoperation,thePLLcontrollerwillonly
changethedivideratiooftheSYSCLKswiththebitsetinDCHANGE.Notethatchangedclockswillbe
automaticallyalignedtootherclocks.ThePLLDIVdividerratiochangestatusregisterisshownin
Figure7-19anddescribedinTable7-27.
3116
Reserved
R-0
1554320
ReservedSYS5SYS4Reserved
R-0R-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-19.PLLDIVDividerRatioChangeStatusRegister(DCHANGE)[HexAddress:029A0144]
Table7-27.PLLDIVDividerRatioChangeStatusRegister(DCHANGE)FieldDescriptions
BitFieldValueDescription
31:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4SYS5IdentifieswhentheSYSCLK5divideratiohasbeenmodified.
0SYSCLK5ratiohasnotbeenmodified.WhenGOSETisset,SYSCLK5willnotbeaffected.
1SYSCLK5ratiohasbeenmodified.WhenGOSETisset,SYSCLK5willchangetothenewratio.
3SYS4IdentifieswhentheSYSCLK4divideratiohasbeenmodified.
0SYSCLK4ratiohasnotbeenmodified.WhenGOSETisset,SYSCLK4willnotbeaffected.
1SYSCLK4ratiohasbeenmodified.WhenGOSETisset,SYSCLK4willchangetothenewratio.
2:0Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
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