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7.7.3.2PLLMultiplierControlRegister
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePLLmultipliercontrolregister(PLLM)isshowninFigure7-12anddescribedinTable7-20.ThePLLM
registerdefinestheinputreferenceclockfrequencymultiplierinconjunctionwiththePLLdividerratiobits
(RATIO)inthePLLcontrollerpre-dividerregister(PREDIV).
3116
Reserved
R-0
15540
ReservedPLLM
R-0R/W-0h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-12.PLLMultiplierControlRegister(PLLM)[HexAddress:029A0110]
Table7-20.PLLMultiplierControlRegister(PLLM)FieldDescriptions
BitFieldValueDescription
31:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4:0PLLMPLLmultiplierbits.Definesthefrequencymultiplieroftheinputreferenceclockinconjunctionwith
thePLLdividerratiobits(RATIO)inPREDIV.
0hx1multiplierrate
Ehx15multiplierrate
13hx20multiplierrate
18hx25multiplierrate
1Dhx30multiplierrate
1Fhx32multiplierrate
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