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SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
C6000DSPplatforms.
SPRU970TMS320C645xDSPDDR2MemoryControllerUser'sGuide.Thisdocumentdescribesthe
DDR2memorycontrollerintheC645xdigital-signalprocessors(DSPs).
SPRU966TMS320C645xDSPEnhancedDMA(EDMA3)ControllerUser'sGuide.Thisdocument
describestheEnhancedDMA(EDMA3)ControllerontheC645xdevice.
SPRU975TMS320C645xDSPEMAC/MDIOModuleUser'sGuide.Thisdocumentprovidesa
functionaldescriptionoftheEthernetMediaAccessController(EMAC)andPhysicallayer
(PHY)deviceManagementDataInput/Output(MDIO)moduleintegratedwiththedevicesof
theC645xfamily.
SPRU971TMS320C645xDSPExternalMemoryInterface(EMIF)User'sGuide.Thisdocument
describestheoperationoftheexternalmemoryinterface(EMIF)inthedigitalsignal
processors(DSPs)oftheC645xDSPfamily.
SPRU724TMS320C645xDSPGeneral-PurposeInput/Output(GPIO)User'sGuide.Thisdocument
describesthegeneral-purposeinput/output(GPIO)peripheralinthedigitalsignalprocessors
(DSPs)oftheC645xDSPfamily.TheGPIOperipheralprovidesdedicatedgeneral-purpose
pinsthatcanbeconfiguredaseitherinputsoroutputs.Whenconfiguredasaninput,you
candetectthestateoftheinputbyreadingthestateofaninternalregister.Whenconfigured
asanoutput,youcanwritetoaninternalregistertocontrolthestatedrivenontheoutput
pin.
SPRU969TMS320C645xDSPHostPortInterface(HPI)User'sGuide.Thisguidedescribesthehost
portinterface(HPI)ontheC645xdigitalsignalprocessors(DSPs).TheHPIenablesan
externalhostprocessor(host)todirectlyaccessDSPresources(includinginternaland
externalmemory)usinga16bit(HPI16)or32bit(HPI32)interface.
SPRU974TMS320C645xDSPInter-IntegratedCircuit(I2C)ModuleUser'sGuide.Thisdocument
describestheinter-integratedcircuit(I2C)moduleintheC645xDigitalSignalProcessor
(DSP).TheI2CprovidesaninterfacebetweentheC645xdeviceandotherdevices
compliantwithPhilipsSemiconductorsInter-ICbus(I2C-bus)specificationversion2.1and
connectedbywayofanI2C-bus.Thisdocumentassumesthereaderisfamiliarwiththe
I2C-busspecification.
SPRUE60TMS320C645xDSPPeripheralComponentInterconnect(PCI)User'sGuide.This
documentdescribestheperipheralcomponentinterconnect(PCI)portinC645xdevices.See
thePCISpecificationrevision2.3fordetailsonthePCIinterface.
SPRU976TMS320C645xDSPSerialRapidI/OUser'sGuide.ThisdocumentdescribestheSerial
RapidIO(SRIO)ontheC645xdevices.
SPRUE56TMS320C645xDSPSoftware-ProgrammablePhase-LockedLoop(PLL)Controller
User'sGuide.Thisdocumentdescribestheoperationofthesoftware-programmable
phase-lockedloop(PLL)controllerintheC645xdigitalsignalprocessors(DSPs).ThePLL
controlleroffersflexibilityandconveniencebywayofsoftware-configurablemultipliersand
dividerstomodifytheinputsignalinternally.Theresultingclockoutputsarepassedtothe
C645xDSPcore,peripherals,andothermodulesinsidetheC645xDSP.
SPRU968TMS320C645xDSP64BitTimerUser'sGuide.Thisdocumentprovidesanoverviewofthe
64bittimerintheC645xDSP.Thetimercanbeconfiguredasageneral-purpose64bit
timer,dualgeneral-purpose32bittimers,orawatchdogtimer.Whenconfiguredasadual
32bittimers,eachhalfcanoperateinconjunction(chainmode)orindependently(unchained
mode)ofeachother.
SPRU973TMS320C645xDSPTurbo-DecoderCoprocessor(TCP)User'sGuide.Channeldecoding
ofhighbit-ratedatachannelsfoundinthirdgeneration(3G)cellularstandardsrequires
decodingofturbo-encodeddata.Theturbo-decodercoprocessor(TCP)insomeofthedigital
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