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7.7.3.3PLLPre-DividerControlRegister
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePLLpre-dividercontrolregister(PREDIV)isshowninFigure7-13anddescribedinTable7-21.
3116
Reserved
R-0
1514540
PREDENReservedRATIO
R/W-1R-0R/W-2h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-13.PLLPre-DividerControlRegister(PREDIV)[HexAddress:029A0114]
Table7-21.PLLPre-DividerControlRegister(PREDIV)FieldDescriptions
BitFieldValueDescription
31:16Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
15PREDENPre-dividerenablebit.
0Pre-dividerisdisabled.Noclockoutput.
1Pre-dividerisenabled.
14:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4:0RATIO0-1FhDividerratiobits.
0÷1.Dividefrequencyby1.
1h÷2.Dividefrequencyby2.
2h÷3.Dividefrequencyby3.
3h-1FhReserved,donotuse.
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