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7.7.4PLL1ControllerInputandOutputClockElectricalData/Timing
CLKIN1
2
3
4
4
5
1
SYSCLK4
3
4
4
2
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
Table7-29.TimingRequirementsforCLKIN1Devices
(1)(2)(3)
(seeFigure7-21)
-720
-850
A-1000/-1000
-1200
NO.UNIT
PLLMODES
x1(Bypass),x15,
x20,x25,x30,x32
MINMAX
1t
c(CLKIN1)
Cycletime,CLKIN1
(4)
1530.3ns
2t
w(CLKIN1H)
Pulseduration,CLKIN1high0.4Cns
3t
w(CLKIN1L)
Pulseduration,CLKIN1low0.4Cns
4t
t(CLKIN1)
Transitiontime,CLKIN11.2ns
5t
J(CLKIN1)
Periodjitter(peak-to-peak),CLKIN1100ps
(1)Thereferencepointsfortheriseandfalltransitionsaremeasuredat3.3VV
IL
MAXandV
IH
MIN.
(2)FormoredetailsonthePLLmultiplierfactors(x1[BYPASS],x15,x20,x25,x30,x32),seeSection7.7.1.2,PLL1ControllerOperating
Modes.
(3)C=CLKIN1cycletimeinns.Forexample,whenCLKIN1frequencyis50MHz,useC=20ns.
(4)ThePLL1multiplierfactors(x1[BYPASS],x15,x20,x25,x30,x32)furtherlimittheMINandMAXvaluesfort
c(CLKIN1)
.Formore
detailedinformationontheselimitations,seeSection7.7.1.1,InternalClocksandMaximumOperatingFrequencies.
Figure7-21.CLKIN1Timing
Table7-30.SwitchingCharacteristicsOverRecommendedOperatingConditionsforSYSCLK4
[CPU/8-CPU/12]
(1)(2)
(seeFigure7-22)
-720
-850
A-1000/-1000
NO.PARAMETERUNIT
-1200
MINMAX
2t
w(CKO3H)
Pulseduration,SYSCLK4high4P–0.76P+0.7ns
3t
w(CKO3L)
Pulseduration,SYSCLK4low4P–0.76P+0.7ns
4t
t(CKO3)
Transitiontime,SYSCLK41ns
(1)Thereferencepointsfortheriseandfalltransitionsaremeasuredat3.3VV
OL
MAXandV
OH
MIN.
(2)P=1/CPUclockfrequencyinnanoseconds(ns)
Figure7-22.SYSCLK4Timing
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