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SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
TheC64x+DSPcoreemployseightfunctionalunits,tworegisterfiles,andtwodatapaths.Liketheearlier
C6000devices,twooftheseeightfunctionalunitsaremultipliersor.Munits.EachC64x+.Munitdoubles
themultiplythroughputversustheC64xcorebyperformingfour16bitx16bitmultiply-accumulates
(MACs)everyclockcycle.Thus,eight16bitx16bitMACscanbeexecutedeverycycleontheC64x+
core.Ata1.2-GHzclockrate,thismeans960016bitMMACscanoccureverysecond.Moreover,each
multiplierontheC64x+corecancomputeone32bitx32bitMACorfour8bitx8bitMACseveryclock
cycle.
TheC6455deviceincludesSerialRapidIO.Thishighbandwidthperipheraldramaticallyimprovessystem
performanceandreducessystemcostforapplicationsthatincludemultipleDSPsonaboard,suchas
videoandtelecominfrastructuresandmedical/imaging.
TheC6455DSPintegratesalargeamountofon-chipmemoryorganizedasatwo-levelmemorysystem.
Thelevel-1(L1)programanddatamemoriesontheC6455deviceare32KBeach.Thismemorycanbe
configuredasmappedRAM,cache,orsomecombinationofthetwo.Whenconfiguredascache,L1
program(L1P)isadirectmappedcachewhereasL1data(L1D)isatwo-waysetassociativecache.The
level2(L2)memoryissharedbetweenprogramanddataspaceandis2096KBinsize.L2memoryalso
canbeconfiguredasmappedRAM,cache,orsomecombinationofthetwo.TheC64x+Megamodulealso
hasa32bitperipheralconfiguration(CFG)port,aninternalDMA(IDMA)controller,asystemcomponent
withreset/bootcontrol,interrupt/exceptioncontrol,apower-downcontrol,andafree-running32bittimer
fortimestamp.
Theperipheralsetincludes:aninter-integratedcircuitbusmodule(I2C);twomultichannelbufferedserial
ports(McBSPs);an8bitUniversalTestandOperationsPHYInterfaceforAsynchronousTransferMode
(ATM)Slave[UTOPIASlave]port;two64bitgeneral-purposetimers(alsoconfigurableasfour32bit
timers);auser-configurable16bitor32bithost-portinterface(HPI16/HPI32);aperipheralcomponent
interconnect(PCI);a16-pingeneral-purposeinput/outputport(GPIO)withprogrammableinterrupt/event
generationmodes;an10/100/1000Ethernetmediaaccesscontroller(EMAC),whichprovidesanefficient
interfacebetweentheC6455DSPcoreprocessorandthenetwork;amanagementdatainput/output
(MDIO)module(alsopartoftheEMAC)thatcontinuouslypollsall32MDIOaddressesinorderto
enumerateallPHYdevicesinthesystem;agluelessexternalmemoryinterface(64bitEMIFA),whichis
capableofinterfacingtosynchronousandasynchronousperipherals;anda32bitDDR2SDRAM
interface.
TheI2CportsontheC6455allowtheDSPtoeasilycontrolperipheraldevicesandcommunicatewitha
hostprocessor.Inaddition,thestandardmultichannelbufferedserialport(McBSP)maybeusedto
communicatewithserialperipheralinterface(SPI)modeperipheraldevices.
TheC6455devicehastwohigh-performanceembeddedcoprocessors[enhancedViterbiDecoder
Coprocessor(VCP2)andenhancedTurboDecoderCoprocessor(TCP2)]thatsignificantlyspeedup
channel-decodingoperationson-chip.TheVCP2operatingatCPUclockdivided-by-3candecodeover
6947.95-Kbpsadaptivemulti-rate(AMR)[K=9,R=1/3]voicechannels.TheVCP2supportsconstraint
lengthsK=5,6,7,8,and9,ratesR=3/4,1/2,1/3,1/4,and1/5andflexiblepolynomials,while
generatingharddecisionsorsoftdecisions.TheTCP2operatingatCPUclockdivided-by-3candecode
uptofifty384-Kbpsoreight2-Mbpsturboencodedchannels(assuming6iterations).TheTCP2
implementsthemax*log-mapalgorithmandisdesignedtosupportallpolynomialsandratesrequiredby
Third-GenerationPartnershipProjects(3GPPand3GPP2),withfullyprogrammableframelengthand
turbointerleaver.Decodingparameterssuchasthenumberofiterationsandstoppingcriteriaarealso
programmable.CommunicationsbetweentheVCP2/TCP2andtheCPUarecarriedoutthroughthe
EDMA3controller.
TheC6455hasacompletesetofdevelopmenttoolswhichincludes:anewCcompiler,anassembly
optimizertosimplifyprogrammingandscheduling,andaWindows®debuggerinterfaceforvisibilityinto
sourcecodeexecution.
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