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7.8.3.1PLLControllerDivider1Register
SM320C6455-EP
FIXED-POINTDIGITALSIGNALPROCESSOR
SPRS462B–SEPTEMBER2007–REVISEDJANUARY2008
ThePLLcontrollerdivider1register(PLLDIV1)isshowninFigure7-24anddescribedinTable7-33.
3116
Reserved
R-0
1514540
D1ENReservedRATIO
R/W-1R-0R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure7-24.PLLControllerDivider1Register(PLLDIV1)[HexAddress:029C0118]
Table7-33.PLLControllerDivider1Register(PLLDIV1)FieldDescriptions
BitFieldValueDescription
31:16Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
15D1ENDividerD1enablebit.
0DividerD1isdisabled.Noclockoutput.
1DividerD1isenabled.
14:5Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
4:0RATIO0-1FhDividerratiobits.
1h÷2.Dividefrequencyby2.
4h÷5.Dividefrequencyby5.
OthersReserved
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