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112 21555 Non-Transparent PCI-to-PCI Bridge User Manual
JTAG Test Port
13.2 Test Access Port Controller
The test access port controller is a finite-state machine that interprets IEEE 1149.1 protocols
received through the tms signal. The state transitions in the controller are caused by the tms signal
on the rising edge of tck. In each state, the controller generates appropriate clock and control
signals that control the operation of the test features. After entry into a state, test feature operations
are initiated on the rising edge of tck.
13.2.1 Initialization
The test access port controller and the instruction register output latches are initialized and JTAG is disabled while the
trst_l input is asserted low (see Figure 26). While signal trst_l is low, the test access port controller enters the
test-logic reset state. This results in the instruction register being reset which holds the bypass register instruction.
During test-logic reset state, all JTAG test logic is disabled, and the device performs normal functions. The test access
port controller leaves this state only after trst_l (low) goes high and an appropriate JTAG test operation sequence is
sent on the tms and tck pins.
For the 21555 to operate properly, the JTAG logic must be reset. The controller will reset:
• Asynchronously with the assertion of trst_l .
• Synchronously after five tck clock cycles, with tms held high.
Note: Prior to normal 21555 operation, this signal must be strobed low or pulled low with a 1k
Ω resistor.
Figure 26. Signal trst_l States
A7805-01
trst_l
JTAG Reset
JTAG Enabled