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68 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Initialization Requirements
6.2.1 Central Function During Reset
The 21555 is selected to be the secondary bus central function when it detects pr_ad[6] low when s_rst_l is
asserted. When the 21555 detects this condition, it immediately drives s_ad, s_cbe_l, and s_par low and tristates
secondary bus control signals for the duration of secondary bus reset. When the 21555 implements a 64-bit
secondary interface, it also asserts s_req64_l, but tristates all other secondary bus 64-bit extension signals.
When pr_ad[6] is detected high during s_rst_l assertion, another device is acting as a central function on the
secondary bus. The 21555 tristates all secondary PCI signals, including s_ad, s_cbe_l, and s_par for the duration
of secondary bus reset. The 21555 does not assert s_req64_l during reset and an external agent must assert
s_req64_l to enable the 21555’s secondary interface 64-bit extension.
Note: The signal s_rst_in_l assertion causes s_rst_l to asynchronously assert. When secondary bus
central functions are enabled, these functions continue to activate upon assertion of s_rst_l.
6.3 21555 Initialization
The 21555 supports the following mechanisms for initialization and configuration:
• Preconfiguration using the SROM interface, this is also called SROM preload.
• Configuration by the local processor through the secondary interface.
• Configuration by the host processor through the primary interface.
Initialization may use all of these mechanisms, or only a subset. Initialization must take place:
• After a hardware reset caused by p_rst_l or s_rst_in_l assertion.
• After device reset caused by setting the Chip Reset bit in the Table 123, “Reset Control Register” on page 188.
• After device reset caused by a power management transition from D3
hot
to D0.
The 21555 reset consists of the following sequence:
1. Signal p_rst_l or s_rst_in_l asserts or the device is reset. The 21555 tristates all PCI outputs and asserts
s_rst_l.
2. Signal p_clk and s_clk start; s_clk_o is a buffered version of p_clk.
3. When pr_ad[6] is low, the 21555 drives s_ad, s_par, and s_cbe_l low for the remainder of s_rst_l assertion,
and asserts s_req64_l.
4. Upon deassertion of p_rst_l or s_rst_in_l, or on the 1st clock cycle following the completion of chip reset:
— The value of pr_ad[3] specifies the value of the
Primary Lockout Reset Value configuration bit upon
completion of reset.
— When pr_ad[4] is low, the 21555 switches into synchronous mode.
— When pr_ad[5] is low, s_clk_o is disabled and driven low.
— When pr_ad[7] is low, the internal arbiter is disabled.
5. The 21555 deasserts s_rst_l after p_rst_l or s_rst_in_l deassertion, or after 100
µs following s_rst_l assertion.