Filter
Top Products
21555 Non-Transparent PCI-to-PCI Bridge User Manual 119
VPD Support 15
This chapter presents the theory of operation information about the 21555 Vital Product Data (VPD) support. See
Chapter 16 for specific information about the VPD registers.
The 21555 provides VPD support through its serial ROM interface. Note that VPD support in the Expansion ROM
as described in the PCI Local Bus Specification, Revision 2.2, is transparent to the 21555 and is not described in this
document.
VPD is stored in the last 3K bits (384 bytes) of the serial ROM. The first 1K bits (128 bytes) of the VPD space are
designated as read only and cannot be written from the VPD serial ROM register interface. The upper 2K bits (256
bytes) are designated as read/write from the VPD serial ROM register interface. Only VPD data can be accessed
through this interface. To read or write any serial ROM location, the CSR serial ROM access mechanism should be
used, as described in Chapter 9 .
15.1 Reading VPD Information
A read can occur to any location in VPD space. Valid VPD byte addresses are 17F:000h. To read VPD information
from the serial ROM, the following steps must be taken:
1. The VPD address and VPD Flag bits are written. This requires a write to bytes E7:E6h, where the low 9 bits
carry the VPD byte address and bit 15 is a 0 (zero), indicating a read operation. The 21555 adds the VPD base
address, 080h, to the VPD byte address to obtain the serial ROM address and perform a read of 4 bytes. The
VPD address has no alignment requirements; it can start on any byte boundary.
2. The VPD Flag bit is polled. When the 21555 returns a 1, the read is complete.
3. The VPD information can be read from the VPD Data register at bytes EB:E8. Byte 0 contains the data at the
location referenced by the VPD Address register. Bytes 3:1 contain successive bytes.
The 21555 always performs a 4-byte read, regardless of the VPD byte address. Therefore, when the VPD byte
address is one of the last 3 bytes in VPD space, the serial ROM address wraps. The remaining 1, 2, or 3 bytes
contain invalid data and should be ignored.
The VPD Address and VPD Data registers should not be written while a VPD read operation is taking place,
otherwise results are unpredictable.