Intel 21555 Network Router User Manual


 
178 21555 Non-Transparent PCI-to-PCI Bridge User Manual
List of Registers
Table 111. ROM Address Register
Byte Offsets: 0CE:0CCh
Bit Name R/W Description
23:0 ROM_ADDR R/W
Contains the byte address of the PROM read or write access used when the
PROM Start bit is set to a 1.
Contains the byte address and Opcode used when the Serial ROM Start bit
is set to a 1. The byte address is contained on bits [8:0]. The opcode is
contained on bits [10:9]. Possible opcode values are:
00: write all, erase all, write enable, programming disable
01: write
10: read
11: erase
Reset value is 000400h (serial ROM read at address 0)
Table 112. ROM Control Register (Sheet 1 of 2)
Byte Offsets: 0CFh
Bit Name R/W Description
0
Serial ROM
Start/Busy
R/W1TS
Starts a serial ROM read, write, or polling operation and returns the
completion status of the access. When written with a 1, performs
the serial ROM operation indicated by the serial ROM opcode. This
bit is automatically cleared by the 21555 when the serial ROM
access is complete. This bit should not be written unless both the
Serial ROM Start and PROM Start bits are 0. Writing a 0 to this bit
has no effect.
When the previous serial ROM operation was a write all, erase all,
write, or erase, writing this bit causes the 21555 to poll the serial
ROM to test for the completion of the operation. The result of the
poll operation is reflected in bit 3 of this register.
Reset value is 0
1 PROM Start/Busy R/W1TS
Starts a PROM read or write operation and returns the completion
status of the access. When written with a 1, the 21555 performs
the PROM operation indicated by the PROM Read/Write Control
bit. This bit is automatically set when the 21555 performs a PROM
read from the Primary Expansion ROM address space. This bit is
automatically cleared by the 21555 when the PROM access is
complete. This bit should not be set unless both the Serial ROM
Start and PROM Start bits are 0. Writing a 0 to this bit has no effect.
Reset value is 0