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21555 Non-Transparent PCI-to-PCI Bridge User Manual 21
Introduction
• Setting a translated base address for a downstream range to fall within an address range defined for upstream
forwarding. This would cause the 21555 to respond as a target on the secondary bus to a downstream
transaction that it has initiated as a master. The transaction would then be forwarded back to the primary bus.
The address on the primary bus depends on the translated base address value for that upstream range.
• Setting a translated base address for an upstream range to fall within an address range for downstream
forwarding. This results in similar behavior described in the previous condition, but in the opposite direction.
• Enabling I/O subtractive decoding in both directions. When an I/O transaction is subtractively decoded on the
primary bus and forwarded downstream by the 21555, and no target responds on the secondary bus, the 21555
subtractively decodes the transaction on the secondary bus and forwards it back upstream. Since there is no
address translation for subtractively decoded I/O transactions, this results in the 21555 forwarding the
transaction downstream and upstream forever.
• Enabling VGA decoding in both directions. Refer to subtractive I/O decoding in the previous bullet. Again,
there is the case of a non translated I/O address decoded by the 21555 on both interfaces as a target and
forwarded to the opposite interface.
2.4.2 Transaction Forwarding
When using the indirect I/O transaction generation mechanism, the low two bits of the I/O address in the I/O
Address register must match the byte enables as described in the PCI Local Bus Specification, Revision 2.2. The
21555 does not correct any discrepancies between the byte enables and address bits [1:0].
2.4.3 ROM Access
Parallel and SROM access mechanisms do not accommodate multiple masters. That is, when more than one master
attempts to access the ROM during the same time period, wrong data may be returned or written to the ROM. There
is no semaphore method to guarantee atomicity of the ROM address, data, and control register accesses.
This also applies to a parallel ROM access through the Primary Expansion ROM BAR at the same time a secondary
bus master might be accessing ROM registers.