Filter
Top Products
44 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Address Decoding
4.4.2 Subtractive Decoding of I/O Transactions
The 21555 can be enabled to subtractively decode I/O transactions and forward these transactions to the opposite
bus. No address translation is performed on subtractively decoded I/O transactions. The transaction is treated by the
21555 as a delayed transaction.
Note: Even when a subtractively-decoded delayed transaction is queued, the 21555 continues to respond
to the transaction on the initiator bus with subtractive timing.
To enable subtractive decoding of I/O transactions on the primary bus, the Subtractive Decode Enable bits in the
Chip Control 1 configuration register must be set to 01b. To enable subtractive decoding of I/O transactions on the
secondary bus, the Subtractive Decode Enable bits must be set to 10b.
There can be only one subtractive decoding agent on a PCI bus. Subtractive decoding should not be enabled for
both the primary and secondary interfaces.
4.5 Configuration Accesses
The 21555 responds to Type 0 configuration transactions on both its primary and secondary interfaces. The 21555
has two sets of configuration registers, one for the primary interface and one for the secondary interface. Both sets
are accessible from either interface. The 21555 can act as an initiator of Type 0 or Type 1 configuration transactions
on the primary or secondary bus using the indirect configuration transaction mechanism.
4.5.1 Type 0 Accesses to 21555 Configuration Space
The 21555 responds as a target to Type 0 configuration transactions on both its primary and secondary interfaces
when the IDSEL pin for that interface is asserted. The 21555 is a single function device so it does not decode the
function number. The 21555 can respond to configuration transactions regardless of the state of the posted write
and delayed transaction queues. Because the 21555 is not a transparent PPB (21154), it does not respond to Type 1
configuration transactions.
Access to the 21555 configuration space may be restricted during different phases of initialization:
• Reset:
No access to the 21555 configuration space from either interface.
• Serial preload:
No access to the 21555 configuration space from either interface. the 21555 returns target retry.
• Optional primary lockout:
Access to the 21555 configuration space is allowed from the secondary interface only, until the Primary
Lockout Bit in the Chip Control 0 register is cleared. The 21555 returns target retry to all accesses initiated on
the primary bus, with the exception of accesses to the Table 123, “Reset Control Register” on page 188 at
Dword D8h.
• Normal configuration and operation:
Access to the 21555 configuration space is allowed from both the primary and secondary interfaces.
See Chapter 2 for a more detailed description of the initialization process.
During normal configuration and operation, when the 21555 decodes a configuration access on one interface while
an access to a configuration register is already ongoing on the other interface, the 21555 holds the second initiator
in wait states until the first transaction is complete, and then completes the second transaction.