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70 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Initialization Requirements
The remainder of the 21555 configuration proceeds as described in Section 6.3.1.
6.3.3 Without Local Processor
Initialization of the 21555 is possible without a local processor, or without local processor intervention. Serial
preload is still performed as described in (Section 16.10). However, the serial load must clear the Primary Lockout
Reset Value bit to allow access of configuration registers from the primary interface. The serial preload must
successfully preconfigure the forwarding BAR setup registers, as well as overwrite primary read-only registers as
necessary.
Upon completion of the serial preload, all configuration registers are accessible for PCI configuration from the host
on the primary bus. The host is then also responsible for configuring the secondary interface and device-specific
configuration registers.
6.3.4 Without Local Processor and Serial Preload
When neither the SROM nor a local processor is present, only the reset values of all the read-only registers are
used, and all forwarding BARs are disabled and do not request space (since all these registers are set up from the
secondary side only). The 21555 configuration registers are accessible, and the 21555 CSR registers can still be
mapped into memory or I/O space. However, the Table 107, “Primary Expansion ROM BAR” on page 175 is
disabled. A parallel ROM (PROM) can still be accessed through the CSR mechanism. Configuration and I/O
transactions can be forwarded through the indirect CSR mechanism; the I20 message unit, doorbell registers, and
scratchpad registers are all accessible. The 21555 configuration registers that are accessible only from the
secondary interface can be written using the downstream indirect configuration mechanism.
6.3.5 Without Host Processor
Initialization of the 21555 can be performed without a host processor. In this case, the local processor must perform
the initialization of the primary configuration registers from the secondary interface.
6.4 Power Management Support
The 21555 implements the PCI Power Management interface on behalf of the subsystem. The 21555 Power
Management interface is designed to be flexible to meet the varying needs of different types of subsystem
functions. To fully understand the PCI Power Management interface, please refer to the PCI Power Management
Specification, Rev 1.0. Some functions may need minimal power management support: the D0 and D3
hot
power
states, without PME# support. Other functions may need all four power states and PME# support. Power
management setup is done by SROM preload.
The SROM preload allows the following power management parameters to be defined:
• Power Management revision number.
• D1 power management state support.
• D2 power management state support.
• PME# support.
• Power Management Data register support.
• Device Specific Initialization status bit.