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21555 Non-Transparent PCI-to-PCI Bridge User Manual 77
Clocking 7
The 21555 supports two clock inputs, p_clk and s_clk. The signal p_clk corresponds to the primary interface and
s_clk corresponds to the secondary interface. Both clocks must adhere to the PCI Local Bus specification.
The 21555 may operate in either synchronous or asynchronous mode. The 21555 starts in asynchronous mode
during reset, but can switch to synchronous mode after reset when pr_ad[4] is sampled low during reset.
In asynchronous mode, p_clk and s_clk can be asynchronous to each other. They can have any phase relationship
and can differ in frequency.
When the 21555 operates in synchronous mode, p_clk and s_clk must operate at the same frequency and have a
fixed phase relationship. Operation in synchronous mode saves at least one clock cycle of latency for transactions
crossing the bridge. In this mode, the skew between p_clk and s_clk rising edges should be no less than 2 ns and no
more than 13 ns (for 66 MHz). Therefore, the s_clk rising edges should never come before p_clk rising edges, and
s_clk rising edges should not follow p_clk rising edges by more than 13 ns.
7.1 Primary and Secondary PCI Bus Clock Signals
Table 20 describes the primary and secondary PCI bus clock and 66 MHz enable signals.
Table 20. Primary and Secondary PCI Bus Clock Signals (Sheet 1 of 2)
Signal Name I/O Description
p_clk I
Primary interface PCI CLK. This signal provides timing for all transactions on the
primary PCI bus. All primary PCI inputs are sampled on the rising edge of p_clk, and
all primary PCI outputs are driven from the rising edge of p_clk. The 21555 operates
in a frequency range from 0 MHz to 66 MHz in synchronous mode. In asynchronous
mode the 21555 supports a clocking ratio (defined p_clk : s_clk or s_clk : p_clk) of a
maximum ratio 2.5 : 1 with the upper frequency limit for either clock input being
66MHz.
p_m66ena I
Primary interface at 66 MHz. Signal p_m66ena asserted high indicates that the
primary interface is operating at 66 MHz.